Patents by Inventor Hiroyuki Nansei
Hiroyuki Nansei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120309138Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.Type: ApplicationFiled: August 10, 2012Publication date: December 6, 2012Inventors: Yukio HAYAKAWA, Hiroyuki NANSEI
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Patent number: 8264029Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.Type: GrantFiled: December 17, 2007Date of Patent: September 11, 2012Assignee: Spansion LLCInventors: Yukio Hayakawa, Hiroyuki Nansei
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Patent number: 8143661Abstract: A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.Type: GrantFiled: October 10, 2006Date of Patent: March 27, 2012Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Takayuki Maruyama, Hidehiko Shiraiwa, Kuo-Tung Chang, Lei Xue, Meng Ding, Amol Ramesh Joshi, YouSeok Suh, Harpreet Sachar
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Publication number: 20110210301Abstract: According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second lines; and a plurality of non-volatile memory cells arranged at positions where the plurality of first lines intersect with the plurality of second lines, wherein each of the plurality of non-volatile memory cells includes a resistance change element and a rectifying element connected in series to the resistance change element, and a resistance change film continuously extending over the plurality of second lines is arranged between the plurality of first lines and the plurality of second lines, and the resistance change element includes a portion where the first line intersect with the second line in the resistance change film.Type: ApplicationFiled: September 16, 2010Publication date: September 1, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Hiroyuki NANSEI
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Publication number: 20110070713Abstract: According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers.Type: ApplicationFiled: September 15, 2010Publication date: March 24, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Hiroyuki Nansei
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Patent number: 7888209Abstract: A semiconductor memory device with the thickness of both a tunnel film and a top film provided thereon configured to be in the FN tunneling region (4 nm or more). Data retention characteristics can be improved by configuring both a tunnel film and a top film to have a thickness in the FN tunneling region. Secondly, a high-concentration impurity region of a conductivity type the same as that of the substrate is provided in a substrate region arranged between assist gates provided adjacently to each other. The aforementioned high-concentration impurity region makes a depletion layer extremely thin when bias is applied to the assist gates. Hot holes generated between bands in the depletion region are injected into a charge storage region and the holes and electrons make pairs and disappear, enabling easy data erasing.Type: GrantFiled: October 7, 2009Date of Patent: February 15, 2011Assignee: Spansion LLCInventor: Hiroyuki Nansei
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Patent number: 7879670Abstract: A method of manufacturing a nonvolatile storage device having memory cell arrays according to an embodiment of the present invention includes forming, in a memory cell array forming region above a processed film, first columnar members arrayed at substantially equal intervals in the first direction and the second direction, forming, concerning at least arrays as a part of arrays of the first columnar members in the first direction, second columnar members long in section having major axes longer than sections of the first columnar members outside of the memory cell array forming region such that the major axes are set in the first direction and the second columnar members continue to ends of the arrays, and forming, in the same manner as above, third columnar members, which continue to arrays of the first columnar members in the second direction.Type: GrantFiled: September 4, 2009Date of Patent: February 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Nansei, Toshiharu Tanaka, Hirokazu Kikuchi
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Publication number: 20100261330Abstract: A method of manufacturing a nonvolatile storage device having memory cell arrays according to an embodiment of the present invention includes forming, in a memory cell array forming region above a processed film, first columnar members arrayed at substantially equal intervals in the first direction and the second direction, forming, concerning at least arrays as a part of arrays of the first columnar members in the first direction, second columnar members long in section having major axes longer than sections of the first columnar members outside of the memory cell array forming region such that the major axes are set in the first direction and the second columnar members continue to ends of the arrays, and forming, in the same manner as above, third columnar members, which continue to arrays of the first columnar members in the second direction.Type: ApplicationFiled: September 4, 2009Publication date: October 14, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki Nansei, Toshiharu Tanaka, Hirokazu Kikuchi
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Patent number: 7675107Abstract: A semiconductor memory device, firstly, has both the thickness of a tunnel film and that of a top film provided thereon and configured to be in the FN tunneling region (4 nm or more). The data retention characteristics can be improved by configuring both the thickness of a tunnel film and that of a top film to have a thickness of in the FN tunneling region. Secondly, a high-concentration impurity region of a conductivity type the same as that of the substrate is provided in a substrate region arranged between assist gates provided adjacently to each other. The aforementioned high-concentration impurity region makes a depletion layer extremely thin when bias is applied to the assist gates. Hot holes generated between bands in the depletion region are injected into a charge storage region and the holes and electrons make pairs and disappear, enabling easy data erasing.Type: GrantFiled: December 27, 2005Date of Patent: March 9, 2010Assignee: Spansion LLCInventor: Hiroyuki Nansei
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Publication number: 20100022081Abstract: A semiconductor memory device with the thickness of both a tunnel film and a top film provided thereon configured to be in the FN tunneling region (4 nm or more). Data retention characteristics can be improved by configuring both a tunnel film and a top film to have a thickness in the FN tunneling region. Secondly, a high-concentration impurity region of a conductivity type the same as that of the substrate is provided in a substrate region arranged between assist gates provided adjacently to each other. The aforementioned high-concentration impurity region makes a depletion layer extremely thin when bias is applied to the assist gates. Hot holes generated between bands in the depletion region are injected into a charge storage region and the holes and electrons make pairs and disappear, enabling easy data erasing.Type: ApplicationFiled: October 7, 2009Publication date: January 28, 2010Inventor: Hiroyuki NANSEI
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Publication number: 20090085213Abstract: A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si3N4.Type: ApplicationFiled: August 27, 2008Publication date: April 2, 2009Inventors: Masahiko HIGASHI, Hiroyuki Nansei
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Publication number: 20090020799Abstract: One embodiment in accordance with the invention can include a semiconductor device that includes: a groove that is formed in a semiconductor substrate; bottom oxide films that are formed on both side faces of the groove; two charge storage layers that are formed on side faces of the bottom oxide films; top oxide films that are formed on side faces of the two charge storage layers; and a silicon oxide layer that is formed on the bottom face of the groove, and has a smaller film thickness than the top oxide films.Type: ApplicationFiled: December 28, 2007Publication date: January 22, 2009Inventor: Hiroyuki Nansei
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Patent number: 7479427Abstract: A semiconductor memory device employs a SONOS type memory architecture and includes a bit line diffusion layer in a shallow trench groove in which a conductive film is buried. This makes it possible to decrease the resistivity of the bit line diffusion layer without enlarging the area on the main surface of the semiconductor substrate, and to fabricate the semiconductor memory device having stable electric characteristics without enlarging the cell area. The bit line is formed by implanting ions into the sidewall of Si3N4.Type: GrantFiled: September 27, 2005Date of Patent: January 20, 2009Assignee: Spansion LLCInventors: Masahiko Higashi, Hiroyuki Nansei
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Publication number: 20080265309Abstract: After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.Type: ApplicationFiled: June 20, 2008Publication date: October 30, 2008Applicant: SPANSION LLCInventors: Masahiko Higashi, Manabu Nakamura, Kentaro Sera, Hiroyuki Nansei, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Publication number: 20080217673Abstract: A semiconductor device includes a stack structure in which multiple channel layers are stacked on a substrate so as to be sandwiched between bit line layers, a gate electrode that is provided to the side of the lateral surface of an interior of a groove portion formed within the stack structure, and a charge storage layer that is provided between the gate electrode and the channel layer.Type: ApplicationFiled: February 5, 2008Publication date: September 11, 2008Applicant: Spansion LLCInventors: Takayuki Maruyama, Yukio Hayakawa, Hiroyuki Nansei
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Patent number: 7410857Abstract: After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.Type: GrantFiled: July 23, 2007Date of Patent: August 12, 2008Assignee: Spansion LLC.Inventors: Masahiko Higashi, Manabu Nakamura, Kentaro Sera, Hiroyuki Nansei, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Publication number: 20080157183Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.Type: ApplicationFiled: December 17, 2007Publication date: July 3, 2008Inventors: Yukio Hayakawa, Hiroyuki Nansei
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Publication number: 20080142874Abstract: A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.Type: ApplicationFiled: December 16, 2006Publication date: June 19, 2008Applicants: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Hidehiko Shiraiwa, Takayuki Maruyama, Kuo-Tung Chang, YouSeok Suh, Amol Ramesh Joshi, Harpreet Sachar, Simon Siu-Sing Chan
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Publication number: 20080083946Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.Type: ApplicationFiled: October 10, 2006Publication date: April 10, 2008Applicants: SPANSION LLC, ADVANCED MICRO DEVICES, INC.Inventors: Shenqing Fang, Rinji Sugino, Jayendra Bhakta, Takashi Orimoto, Hiroyuki Nansei, Yukio Hayakawa, Takayuki Maruyama, Hidehiko Shiraiwa, Kuo-Tung Chang, Lei Xue, Meng Ding, Amol Ramesh Joshi, YouSeok Suh, Harpreet Sachar
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Publication number: 20070262374Abstract: After an ONO film in which a silicon nitride film (22) formed by a plasma nitriding method using a plasma processor having a radial line slot antenna is sandwiched by silicon oxide films (21), (23), a bit line diffusion layer (17) is formed in a memory cell array region (11) by an ion implantation as a resist pattern (16) taken as a mask, then lattice defects are given to the silicon nitride film (22) by a further ion implantation. Accordingly, a highly reliable semiconductor memory device can be realized, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.Type: ApplicationFiled: July 23, 2007Publication date: November 15, 2007Applicant: SPANSION LLCInventors: Masahiko Higashi, Manabu Nakamura, Kentaro Sera, Hiroyuki Nansei, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita