Patents by Inventor Hiroyuki Nihira

Hiroyuki Nihira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5244822
    Abstract: In a bipolar transistor, having a micronized structure for a high-speed LSI, which is fabricated by a self-alignment technology, a barrier insulating film is buried in a portion around an emitter layer so as to be deeper than a junction level between an active base layer and a collector layer. When a polysilicon film pattern which defines an active base region and serves as a portion of a base electrode is formed on a wafer surface, a surface portion of a photoresist serving as an etching mask is converted to a carbonized layer by ion implantation. When a micronized emitter layer is formed by a polysilicon-emitter technology, ion implantation is performed before deposition of the polysilicon film or an impurity is doped in the polysilicon film simultaneously with deposition, and rapid thermal annealing is performed so as to activate the doped impurity.
    Type: Grant
    Filed: January 8, 1992
    Date of Patent: September 14, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nihira, Nobuyuki Itoh, Hiroomi Nakajima, Eiryo Tsukioka, Toshio Yamaguchi
  • Patent number: 5204276
    Abstract: In the method of manufacturing a semiconductor device, a buffer oxide film, an oxidation-resistant film and a first poly-Si film containing a p-type impurity are successively formed to form a laminate structure on the n-type collector region, followed by forming a protective oxide film by CVD. Then, an opening portion reaching the oxidation-resistant film is formed, followed by forming a second protective insulation film to cover the surface of the first poly-Si film exposed at the side wall of the opening portion. The oxidation-resistant film is excessively etched using the protective insulation films as an etching mask so as to expose the buffer oxide film and to form a bore below the first poly-Si film. The exposed buffer oxide film is removed, followed by filling the bore with a second poly-Si film. Then, a heat treatment is performed under an oxidative atmosphere to form a thermal oxide film covering the surface of the second poly-Si film.
    Type: Grant
    Filed: January 24, 1991
    Date of Patent: April 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroomi Nakajima, Nobuyuki Itoh, Hiroyuki Nihira, Eiryo Tsukioka, Kenji Hirakawa, Shin-ichi Taka, Hideki Takada, Yasuhiro Katsumata, Toshio Yamaguchi
  • Patent number: 5100813
    Abstract: A method of manufacturing a bipolar transistor. A first mask material film pattern is formed on an internal base region prospective portion on a collector region of a first conductive type, and then a first conductive film is deposited. A recess around the projection of the mask film pattern are transferred on the surface of the first conductive film. After a second mask material film pattern is buried in the recess, the first conductive film is selectively etched using the second mask material pattern as a mask, thereby exposing the first mask material film pattern. The first conductive film is continuously, selectively etched by anisotropic etching using the exposed first mask material film pattern and the second mask material film pattern as etching masks to form a first opening between the two mask material film patterns. An impurity of a second conductivity type is doped in the wafer through the first opening to form an external base region of the second conductivity type.
    Type: Grant
    Filed: January 19, 1990
    Date of Patent: March 31, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nihira, Nobuyuki Itoh
  • Patent number: 5096842
    Abstract: In a bipolar transistor, having a micronized structure for a high-speed LSI, which is fabricated by a self-alignment technology, a barrier insulating film is buried in a portion around an emitter layer so as to be deeper than a junction level between an active base layer and a collector layer. When a polysilicon film pattern which defines an active base region and serves as a portion of a base electrode is formed on a wafer surface, a surface portion of a photoresist serving as an etching mask is converted to a carbonized layer by ion implantation. When a micronized emitter layer is formed by a polysilicon-emitter technology, ion implantation is performed before deposition of the polysilicon film or an impurity is doped in the polysilicon film simultaneously with deposition, and rapid thermal annealing is performed so as to activate the doped impurity.
    Type: Grant
    Filed: May 9, 1989
    Date of Patent: March 17, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nihira, Nobuyuki Itoh, Hiroomi Nakajima, Eiryo Tsukioka, Toshio Yamaguchi
  • Patent number: 4931409
    Abstract: A method of manufacturing a semiconductor device comprising steps of forming a trench on a semiconductor substrate, forming a first film on the surface of the semiconductor substrate so as to have a large thickness on an upper portion of a side surface of the trench, and to have a small thickness on a bottom portion of the trench, selectively doping an impurity in the bottom portion of the trench through a thin portion of the first film formed on the bottom portion of the trench to form an impurity region on the bottom portion of the trench, removing the first film, and forming a second film having an insulating property on the surface of the semiconductor substrate. A dielectric material or conductive material layer is formed in the trench in which the second film is formed on the inner surface. When the dielectric material or the conductive material layer is formed in the trench, a method of this invention can be applied to formation of trench isolation.
    Type: Grant
    Filed: January 30, 1989
    Date of Patent: June 5, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroomi Nakajima, Nobuyuki Itoh, Hiroyuki Nihira
  • Patent number: 4908324
    Abstract: A method of manufacturing a bipolar transistor is disclosed. A first mask material film pattern is formed on an internal base region prospective portion on a collector region of a first conductive type, and then a first conductive film is deposited. A recess around the projection of the mask film pattern are transferred on the surface of the first conductive film. After a second mask material film pattern is buried in the recess, the first conductive film is selectively etched using the second mask material pattern as a mask, thereby exposing the first mask material film pattern. The first conductive film is continuously, selectively etched by anisotropic etching using the exposed first mask material film pattern and the second mask material film pattern as etching masks to form a first opening between the two mask material film patterns. An impurity of a second conductivity type is doped through the first opening to form an external base region.
    Type: Grant
    Filed: July 29, 1988
    Date of Patent: March 13, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nihira, Nobuyuki Itoh