Abstract: An output buffer circuit for an LSI circuit includes a control signal generating circuit, responsive to a signal at either one of first and second levels from an internal logic circuit for generating a control voltage at a level which is sufficient to reliably turn off the PMOSFET of a first CMOS circuit in the output buffer circuit. When the PMOSFET of the first CMOS circuit is turned off, a feedback circuit applies to the gate electrode of the PMOSFET, a signal at a level sufficient to maintain the PMOSFET in the non-conductive state regardless of changes in the control voltage while the signal from the internal logic circuit is at above-stated one level.