Abstract: A capacitor having a MIM structure includes a dielectric formed by laminating a plurality of times on an upper surface of a lower electrode, and an upper electrode on an upper surface of the dielectric. Forming of the dielectric includes forming the first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming the second dielectric layer on an upper surface of the cleaned first dielectric layer.

Abstract: A method for inspecting a surface of a wafer, includes steps of: irradiating a surface of the wafer with a laser beam having three or more distinct wavelengths; detecting a reflected light from the surface of the wafer when the surface of the wafer is irradiated with the laser beam; and determining whether a foreign matter exists on the surface of the wafer based on reflectances of the surface of the wafer with respect to the laser beam having the three or more distinct wavelengths, wherein the step of determining whether the foreign matter exists includes a step of determining whether the foreign matter is a metal or a non-metal.

Abstract: A capacitor having a MIM structure includes a dielectric formed by laminating a plurality of times on an upper surface of a lower electrode, and an upper electrode on an upper surface of the dielectric. Forming of the dielectric includes forming the first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming the second dielectric layer on an upper surface of the cleaned first dielectric layer.

Abstract: A method of manufacturing a capacitor having an MIM structure includes forming a dielectric by laminating a plurality of times on an upper surface of a lower electrode, and forming an upper electrode on an upper surface of the dielectric. The forming of the dielectric includes forming a first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming a second dielectric layer on the cleaned upper surface of the first dielectric layer.

Abstract: A method for inspecting a surface of a wafer, includes steps of: irradiating a surface of the wafer with a laser beam having three or more distinct wavelengths; detecting a reflected light from the surface of the wafer when the surface of the wafer is irradiated with the laser beam; and determining whether a foreign matter exists on the surface of the wafer based on reflectances of the surface of the wafer with respect to the laser beam having the three or more distinct wavelengths, wherein the step of determining whether the foreign matter exists includes a step of determining whether the foreign matter is a metal or a non-metal.

Abstract: A method of manufacturing a capacitor having an MIM structure includes forming a dielectric by laminating it a plurality of times on an upper surface of a lower electrode, and forming an upper electrode on an upper surface of the dielectric. The forming of the dielectric includes forming the first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming the second dielectric layer on an upper surface of the cleaned first dielectric layer.

Abstract: A fabrication method of a semiconductor device includes forming a silicon nitride layer on a compound semiconductor layer with a plasma CVD method and selectively treating the compound semiconductor layer with use of the silicon nitride layer for a mask. The silicon nitride layer has a refraction index of less than 1.85. The compound semiconductor layer includes Ga.

Abstract: A fabrication method of a semiconductor device includes forming a silicon nitride layer on a compound semiconductor layer with a plasma CVD method and selectively treating the compound semiconductor layer with use of the silicon nitride layer for a mask. The silicon nitride layer has a refraction index of less than 1.85. The compound semiconductor layer includes Ga.

Abstract: A hetero-junction bipolar transistor includes a collector layer, a base layer and an emitter layer, an emitter electrode containing Au being provided for the emitter layer, and an Au-diffusion barrier layer of InP or InGaP interposed between the emitter electrode and the base layer.

Abstract: A hetero-junction bipolar transistor includes a collector layer, a base layer and an emitter layer, an emitter electrode containing Au being provided for the emitter layer, and an Au-diffusion barrier layer of InP or InGaP interposed between the emitter electrode and the base layer.

Abstract: This invention relates to a method for recycling a polyester chip which comprises providing a polyester chip (a), polyol (b) and polybasic acid (c), subjecting said (a) and said (b) to transesterification reaction and reacting it with said (c) to give a reconstituted polyester resin, the total number of moles of hydroxyl group being not less than 1.03 times the total number of moles of carboxyl group in the material for the production of said reconstituted polyester resin; and a method for recycling a polyester chip which comprises providing said (a), (b) and (c) and, with the total of (a), (b) and (c), subjecting said (a) and said (c) to transesterification reaction and reacting it with said (b) to give a reconstituted polyester resin, the total number of moles of hydroxyl group being not less than 1.03 times the total number of moles of carboxyl group in the material for the production of said reconstituted polyester resin.

Abstract: A field effect transistor has a semiconductor lamination structure, a Schottky contact gate electrode and source/drain ohmic electrodes disposed on both sides of the gate electrode on the lamination structure, source/drain regions disposed under the source/drain electrodes, a channel layer disposed in the lamination structure spaced apart from the principal surface and connecting the source/drain regions, a barrier layer disposed in the lamination structure between the channel layer and the principal surface and having a conduction band edge energy higher than the channel layer, and a pair of impurity doped regions formed in the barrier layer and channel layer continuously with the source/drain regions on both sides of the gate electrode, wherein a carrier density in the barrier layer is lower than a carrier density in the channel layer in the impurity doped region.

Abstract: An enhancement-mode semiconductor device includes a barrier layer formed on a channel layer and a gate electrode provided on the barrier layer, wherein the gate electrode is formed with an orientation chosen so as to maximize a threshold voltage of the semiconductor device.

Abstract: A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.

Abstract: A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.