Patents by Inventor Hiroyuki Oguri

Hiroyuki Oguri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11965499
    Abstract: A motor includes: a central shaft; a stator extending in an axial direction around the central shaft; a rotor facing an outer side in a radial direction of the stator and configured to rotate around the central shaft; a substrate located on one side in the axial direction with respect to the rotor and on which a rotation position detection circuit detecting a rotation position of the rotor is mounted; and a case located on one side in the axial direction with respect to the substrate and supporting the stator. The stator includes a restricting portion restricting a position in a circumferential direction of the substrate. The case includes a fixing portion fixing the substrate. The substrate includes a restricted portion whose position in the circumferential direction is restricted by the restricting portion, and a fixed portion fixed to the fixing portion.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: April 23, 2024
    Assignee: Max Co., Ltd.
    Inventors: Hiroyuki Tanaka, Takashi Ando, Tomohide Tsutsui, Hisami Oguri
  • Patent number: 11561186
    Abstract: A method for inspecting a surface of a wafer, includes steps of: irradiating a surface of the wafer with a laser beam having three or more distinct wavelengths; detecting a reflected light from the surface of the wafer when the surface of the wafer is irradiated with the laser beam; and determining whether a foreign matter exists on the surface of the wafer based on reflectances of the surface of the wafer with respect to the laser beam having the three or more distinct wavelengths, wherein the step of determining whether the foreign matter exists includes a step of determining whether the foreign matter is a metal or a non-metal.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 24, 2023
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Hiroyuki Oguri
  • Publication number: 20210335992
    Abstract: A capacitor having a MIM structure includes a dielectric formed by laminating a plurality of times on an upper surface of a lower electrode, and an upper electrode on an upper surface of the dielectric. Forming of the dielectric includes forming the first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming the second dielectric layer on an upper surface of the cleaned first dielectric layer.
    Type: Application
    Filed: July 7, 2021
    Publication date: October 28, 2021
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Yoshihide KOMATSU, Takeshi IGARASHI, HIroyuki OGURI
  • Patent number: 11152457
    Abstract: A method of manufacturing a capacitor having an MIM structure includes forming a dielectric by laminating a plurality of times on an upper surface of a lower electrode, and forming an upper electrode on an upper surface of the dielectric. The forming of the dielectric includes forming a first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming a second dielectric layer on the cleaned upper surface of the first dielectric layer.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 19, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Yoshihide Komatsu, Takeshi Igarashi, Hiroyuki Oguri
  • Publication number: 20200400587
    Abstract: A method for inspecting a surface of a wafer, includes steps of: irradiating a surface of the wafer with a laser beam having three or more distinct wavelengths; detecting a reflected light from the surface of the wafer when the surface of the wafer is irradiated with the laser beam; and determining whether a foreign matter exists on the surface of the wafer based on reflectances of the surface of the wafer with respect to the laser beam having the three or more distinct wavelengths, wherein the step of determining whether the foreign matter exists includes a step of determining whether the foreign matter is a metal or a non-metal.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 24, 2020
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Hiroyuki OGURI
  • Publication number: 20190355805
    Abstract: A method of manufacturing a capacitor having an MIM structure includes forming a dielectric by laminating it a plurality of times on an upper surface of a lower electrode, and forming an upper electrode on an upper surface of the dielectric. The forming of the dielectric includes forming the first dielectric layer on the upper surface of the lower electrode, cleaning an upper surface of the first dielectric layer by at least one of jet cleaning and dual fluid cleaning, and forming the second dielectric layer on an upper surface of the cleaned first dielectric layer.
    Type: Application
    Filed: May 14, 2019
    Publication date: November 21, 2019
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Yoshihide KOMATSU, Takeshi IGARASHI, Hiroyuki OGURI
  • Patent number: 7838444
    Abstract: A fabrication method of a semiconductor device includes forming a silicon nitride layer on a compound semiconductor layer with a plasma CVD method and selectively treating the compound semiconductor layer with use of the silicon nitride layer for a mask. The silicon nitride layer has a refraction index of less than 1.85. The compound semiconductor layer includes Ga.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: November 23, 2010
    Assignee: Eudyna Devices Inc.
    Inventor: Hiroyuki Oguri
  • Publication number: 20070167031
    Abstract: A fabrication method of a semiconductor device includes forming a silicon nitride layer on a compound semiconductor layer with a plasma CVD method and selectively treating the compound semiconductor layer with use of the silicon nitride layer for a mask. The silicon nitride layer has a refraction index of less than 1.85. The compound semiconductor layer includes Ga.
    Type: Application
    Filed: January 18, 2007
    Publication date: July 19, 2007
    Applicant: EUDYNA DEVICES INC.
    Inventor: Hiroyuki Oguri
  • Patent number: 6781165
    Abstract: A hetero-junction bipolar transistor includes a collector layer, a base layer and an emitter layer, an emitter electrode containing Au being provided for the emitter layer, and an Au-diffusion barrier layer of InP or InGaP interposed between the emitter electrode and the base layer.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: August 24, 2004
    Assignee: Fujitsu Quantum Devices Limited
    Inventor: Hiroyuki Oguri
  • Publication number: 20030183846
    Abstract: A hetero-junction bipolar transistor includes a collector layer, a base layer and an emitter layer, an emitter electrode containing Au being provided for the emitter layer, and an Au-diffusion barrier layer of InP or InGaP interposed between the emitter electrode and the base layer.
    Type: Application
    Filed: January 22, 2003
    Publication date: October 2, 2003
    Applicant: FUJITSU QUANTUM DEVICES LIMITED
    Inventor: Hiroyuki Oguri
  • Patent number: 6429233
    Abstract: This invention relates to a method for recycling a polyester chip which comprises providing a polyester chip (a), polyol (b) and polybasic acid (c), subjecting said (a) and said (b) to transesterification reaction and reacting it with said (c) to give a reconstituted polyester resin, the total number of moles of hydroxyl group being not less than 1.03 times the total number of moles of carboxyl group in the material for the production of said reconstituted polyester resin; and a method for recycling a polyester chip which comprises providing said (a), (b) and (c) and, with the total of (a), (b) and (c), subjecting said (a) and said (c) to transesterification reaction and reacting it with said (b) to give a reconstituted polyester resin, the total number of moles of hydroxyl group being not less than 1.03 times the total number of moles of carboxyl group in the material for the production of said reconstituted polyester resin.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: August 6, 2002
    Assignee: Nippon Paint Co., Ltd.
    Inventors: Hiroyuki Oguri, Masahiro Matsumoto, Hirotoshi Umemoto
  • Patent number: 6329677
    Abstract: A field effect transistor has a semiconductor lamination structure, a Schottky contact gate electrode and source/drain ohmic electrodes disposed on both sides of the gate electrode on the lamination structure, source/drain regions disposed under the source/drain electrodes, a channel layer disposed in the lamination structure spaced apart from the principal surface and connecting the source/drain regions, a barrier layer disposed in the lamination structure between the channel layer and the principal surface and having a conduction band edge energy higher than the channel layer, and a pair of impurity doped regions formed in the barrier layer and channel layer continuously with the source/drain regions on both sides of the gate electrode, wherein a carrier density in the barrier layer is lower than a carrier density in the channel layer in the impurity doped region.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: December 11, 2001
    Assignee: Fujitsu Quantum Devices Limited
    Inventors: Hiroyuki Oguri, Teruo Yokoyama
  • Patent number: 6278141
    Abstract: An enhancement-mode semiconductor device includes a barrier layer formed on a channel layer and a gate electrode provided on the barrier layer, wherein the gate electrode is formed with an orientation chosen so as to maximize a threshold voltage of the semiconductor device.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: August 21, 2001
    Assignee: Fujitsu Limited
    Inventors: Eizo Mitani, Hiroyuki Oguri
  • Patent number: 6153897
    Abstract: A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: November 28, 2000
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Oguri, Teruo Yokoyama
  • Patent number: 5837617
    Abstract: A laminated layer having a layer containing Al (In) and a layer not containing Al (In) alternately laminated one upon another is plasma etched by an etchant gas which can etch both the layers containing and not containing Al (In). An additive gas containing F is added to the etchant gas while a layer not containing Al (In) is etched. When the surface of the layer containing Al (In) is exposed, fluorides are formed on the surface of the layer containing Al (In) and the etching is automatically stopped. An emission peak specific to Al (In) is monitored to detect which layer is presently etched.
    Type: Grant
    Filed: April 1, 1994
    Date of Patent: November 17, 1998
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Oguri, Teruo Yokoyama