Patents by Inventor Hiroyuki Ohkawa
Hiroyuki Ohkawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10336485Abstract: A binding machine for gardening includes a binding machine main body, a magazine attached to the binding machine main body and loaded with a tape, and a clincher arm rotatably attached to the binding machine main body and configured to draw the tape out of the magazine and bind an object to be bound which is wound by the tape. The magazine includes a housing in which the tape is loaded, a boss provided at a center of the housing and configured to support a reel around which the tape is wound, and an abutting member rotatably attached to the boss and abuts against an inner peripheral surface of the reel.Type: GrantFiled: June 14, 2017Date of Patent: July 2, 2019Assignee: MAX CO., LTD.Inventors: Hajime Takemura, Hiroyuki Ohkawa
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Patent number: 10241369Abstract: An object of the present invention is to realize a display device having a layered wiring structure, that is capable of detecting leakage without fail by using a simple testing circuit. Source bus lines (SL) are wired such that, in the layered region, two source bus lines (SL) adjacent in a vertical direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column, and two source bus lines (SL) adjacent in a horizontal direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column. Potentials of different magnitudes are supplied respectively to source bus lines (SL) of odd-numbered columns and source bus lines (SL) of even-numbered columns via testing lines.Type: GrantFiled: November 13, 2015Date of Patent: March 26, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Etsuo Yamamoto, Hiroyuki Ohkawa, Shige Furuta
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Patent number: 10228595Abstract: In a display device having a layered wiring structure of P layers, and employing a Q-column reversal driving method in which a polarity of a video signal is reversed every Q source bus lines, the plurality of source bus lines are wired to the plurality of layers such that taking source bus lines of a number equal to a double of a least common multiple of P and Q as one group, the number of source bus lines to which positive video signals are applied matches the number of source bus lines to which negative video signals are applied in each of the layers in each of horizontal scanning periods.Type: GrantFiled: November 13, 2015Date of Patent: March 12, 2019Assignee: SHARP KABUSHIKI KAISHAInventors: Etsuo Yamamoto, Hiroyuki Ohkawa, Shige Furuta
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Patent number: 10189739Abstract: To provide chemically tempered glass which is less likely to break even if scratched. Chemically tempered glass, which comprises, as represented by mole percentage based on the following oxides, from 56 to 72% of SiO2, from 8 to 20% of Al2O3, from 9 to 25% of Na2O, from 0 to 2% of K2O, and from 0 to 15% of MgO, and which has a surface compressive stress of at least 900 MPa and an internal tensile stress of at most 30 MPa. Glass for chemical tempering, which comprises, as represented by mole percentage based on the following oxides, from 56 to 69% of SiO2, from 8 to 16% of Al2O3, from 9 to 22% of Na2O, from 0 to 1% of K2O, from 5.5 to 14% of MgO, from 0 to 2% of ZrO2, and from 0 to 6% of B2O3.Type: GrantFiled: November 30, 2017Date of Patent: January 29, 2019Assignee: AGC Inc.Inventors: Shusaku Akiba, Shigeki Sawamura, Suguru Murayama, Hiroyuki Ohkawa, Yusuke Kobayashi, Kazutaka Ono, Tetsuya Nakashima
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Publication number: 20180230045Abstract: A glass resin laminate includes a sheet glass having a compressive stress layer formed in a main surface thereof and a resin layer provided on the sheet glass. A surface compressive stress in the main surface of the sheet glass is 200 MPa or more. A depth of the compressive stress layer is 3 ?m or more. A central tension CT (MPa) and a sheet thickness t (mm) of the sheet glass satisfy the equations CT?64.1× t?0.703 (4) and CT>?38.7×ln(t)+48.2 (5).Type: ApplicationFiled: April 13, 2018Publication date: August 16, 2018Applicant: ASAHI GLASS COMPANY, LIMITEDInventor: Hiroyuki OHKAWA
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Patent number: 9928794Abstract: A shift register according to the present invention is a shift register in which a plurality of unit circuits are connected in cascade, wherein the unit circuit includes a first output transistor whose current path is connected between an output terminal and a clock terminal to which a first clock signal is provided; a second output transistor whose current path is connected between the output terminal and a predetermined potential node; a setting device which, when a control signal is active, sets a signal level of the output terminal to a predetermined signal level; a first output control device which provides a signal level of the control signal to a control electrode of the first output transistor to turn off the first output transistor when the control signal is active; and a second output control device which turns off the second output transistor when the control signal is active.Type: GrantFiled: July 18, 2014Date of Patent: March 27, 2018Assignee: Sharp Kabushiki KaishaInventors: Hiroyuki Ohkawa, Shige Furuta, Yuhichiroh Murakami
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Publication number: 20180079680Abstract: To provide chemically tempered glass which is less likely to break even if scratched. Chemically tempered glass, which comprises, as represented by mole percentage based on the following oxides, from 56 to 72% of SiO2, from 8 to 20% of Al2O3, from 9 to 25% of Na2O, from 0 to 2% of K2O, and from 0 to 15% of MgO, and which has a surface compressive stress of at least 900 MPa and an internal tensile stress of at most 30 MPa. Glass for chemical tempering, which comprises, as represented by mole percentage based on the following oxides, from 56 to 69% of SiO2, from 8 to 16% of Al2O3, from 9 to 22% of Na2O, from 0 to 1% of K2O, from 5.5 to 14% of MgO, from 0 to 2% of ZrO2, and from 0 to 6% of B2O3.Type: ApplicationFiled: November 30, 2017Publication date: March 22, 2018Applicant: ASAHI GLASS COMPANY, LIMITEDInventors: Shusaku AKIBA, Shigeki SAWAMURA, Suguru MURAYAMA, Hiroyuki OHKAWA, Yusuke KOBAYASHI, Kazutaka ONO, Tetsuya NAKASHIMA
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Patent number: 9896374Abstract: To provide chemically tempered glass which is less likely to break even if scratched. Chemically tempered glass, which comprises, as represented by mole percentage based on the following oxides, from 56 to 72% of SiO2, from 8 to 20% of Al2O3, from 9 to 25% of Na2O, from 0 to 2% of K2O, and from 0 to 15% of MgO, and which has a surface compressive stress of at least 900 MPa and an internal tensile stress of at most 30 MPa. Glass for chemical tempering, which comprises, as represented by mole percentage based on the following oxides, from 56 to 69% of SiO2, from 8 to 16% of Al2O3, from 9 to 22% of Na2O, from 0 to 1% of K2O, from 5.5 to 14% of MgO, from 0 to 2% of ZrO2, and from 0 to 6% of B2O3.Type: GrantFiled: March 9, 2017Date of Patent: February 20, 2018Assignee: Asahi Glass Company, LimitedInventors: Shusaku Akiba, Shigeki Sawamura, Suguru Murayama, Hiroyuki Ohkawa, Yusuke Kobayashi, Kazutaka Ono, Tetsuya Nakashima
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Publication number: 20180044232Abstract: The present invention provides a cover glass for a display, having high durability to slow cracking and strong abraded strength even though a compressive stress is large and a depth of a compressive stress layer is deep. The present invention relates to a cover glass for a display, in which a depth of a compressive stress layer (DOL) is 30 ?m or more, a surface compressive stress is 300 MPa or more, a position (HW) at which a compressive stress is half of a value of the surface compressive stress is a position of 8 ?m or more from a glass surface, and the depth of the compressive stress layer (DOL) and the position (HW) at which the compressive stress is half of the value of the surface compressive stress satisfy the following formula: 0.05?HW/DOL?0.23??(1).Type: ApplicationFiled: October 5, 2017Publication date: February 15, 2018Applicant: ASAHI GLASS COMPANY, LIMITEDInventors: Seiki OHARA, Kazutaka ONO, Tetsuya NAKASHIMA, Hiroyuki OHKAWA
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Publication number: 20180037498Abstract: The present invention provides a cover glass for a display, having high durability to slow cracking and strong abraded strength even though a compressive stress is large and a depth of a compressive stress layer is deep. The present invention relates to a cover glass for a display, in which a depth of a compressive stress layer (DOL) is 30 ?m or more, a surface compressive stress is 300 MPa or more, a position (HW) at which a compressive stress is half of a value of the surface compressive stress is a position of 8 ?m or more from a glass surface, and the depth of the compressive stress layer (DOL) and the position (HW) at which the compressive stress is half of the value of the surface compressive stress satisfy the following formula: 0.05?HW/DOL?0.23??(1).Type: ApplicationFiled: September 1, 2017Publication date: February 8, 2018Applicant: ASAHI GLASS COMPANY, LIMITEDInventors: Seiki Ohara, Kazutaka Ono, Tetsuya Nakashima, Hiroyuki Ohkawa
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Publication number: 20170361957Abstract: A binding machine for gardening includes a binding machine main body, a magazine attached to the binding machine main body and loaded with a tape, and a clincher arm rotatably attached to the binding machine main body and configured to draw the tape out of the magazine and bind an object to be bound which is wound by the tape. The magazine includes a housing in which the tape is loaded, a boss provided at a center of the housing and configured to support a reel around which the tape is wound, and an abutting member rotatably attached to the boss and abuts against an inner peripheral surface of the reel.Type: ApplicationFiled: June 14, 2017Publication date: December 21, 2017Applicant: MAX CO., LTD.Inventors: Hajime TAKEMURA, Hiroyuki OHKAWA
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Patent number: 9840435Abstract: The present invention provides a cover glass for a display, having high durability to slow cracking and strong abraded strength even though a compressive stress is large and a depth of a compressive stress layer is deep. The present invention relates to a cover glass for a display, in which a depth of a compressive stress layer (DOL) is 30 ?m or more, a surface compressive stress is 300 MPa or more, a position (HW) at which a compressive stress is half of a value of the surface compressive stress is a position of 8 ?m or more from a glass surface, and the depth of the compressive stress layer (DOL) and the position (HW) at which the compressive stress is half of the value of the surface compressive stress satisfy the following formula: 0.05?HW/DOL?0.23??(1).Type: GrantFiled: June 11, 2014Date of Patent: December 12, 2017Assignee: ASAHI GLASS COMPANY, LIMITEDInventors: Seiki Ohara, Kazutaka Ono, Tetsuya Nakashima, Hiroyuki Ohkawa
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Publication number: 20170336667Abstract: An object of the present invention is to realize a display device having a layered wiring structure, that is capable of detecting leakage without fail by using a simple testing circuit. Source bus lines (SL) are wired such that, in the layered region, two source bus lines (SL) adjacent in a vertical direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column, and two source bus lines (SL) adjacent in a horizontal direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column. Potentials of different magnitudes are supplied respectively to source bus lines (SL) of odd-numbered columns and source bus lines (SL) of even-numbered columns via testing lines.Type: ApplicationFiled: November 13, 2015Publication date: November 23, 2017Inventors: Etsuo YAMAMOTO, Hiroyuki OHKAWA, Shige FURUTA
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Publication number: 20170336688Abstract: An object of the present invention is to suppress deterioration of display quality due to difference in wiring resistance and capacitance between the layers in a display device having a layered wiring structure. In a display device having a layered wiring structure of P layers, and employing a Q-column reversal driving method in which a polarity of a video signal is reversed every Q source bus lines (SL), the plurality of source bus lines SL are wired to the plurality of layers such that taking source bus lines (SL) of a number equal to a double of a least common multiple of P and Q as one group, the number of source bus lines (SL) to which positive video signals are applied matches the number of source bus lines (SL) to which negative video signals are applied in each of the layers in each of horizontal scanning periods.Type: ApplicationFiled: November 13, 2015Publication date: November 23, 2017Inventors: Etsuo YAMAMOTO, Hiroyuki OHKAWA, Shige FURUTA
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Publication number: 20170217824Abstract: The present invention provides a cover glass for a display, having high durability to slow cracking and strong abraded strength even though a compressive stress is large and a depth of a compressive stress layer is deep. The present invention relates to a cover glass for a display, in which a depth of a compressive stress layer (DOL) is 30 ?m or more, a surface compressive stress is 300 MPa or more, a position (HW) at which a compressive stress is half of a value of the surface compressive stress is a position of 8 ?m or more from a glass surface, and the depth of the compressive stress layer (DOL) and the position (HW) at which the compressive stress is half of the value of the surface compressive stress satisfy the following formula: 0.05?HW/DOL?0.23??(1).Type: ApplicationFiled: April 7, 2017Publication date: August 3, 2017Applicant: ASAHI GLASS COMPANY, LIMITEDInventors: SEIKI OHARA, KAZUTAKA ONO, TETSUYA NAKASHIMA, HIROYUKI OHKAWA
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Publication number: 20170183254Abstract: To provide chemically tempered glass which is less likely to break even if scratched. Chemically tempered glass, which comprises, as represented by mole percentage based on the following oxides, from 56 to 72% of SiO2, from 8 to 20% of Al2O3, from 9 to 25% of Na2O, from 0 to 2% of K2O, and from 0 to 15% of MgO, and which has a surface compressive stress of at least 900 MPa and an internal tensile stress of at most 30 MPa. Glass for chemical tempering, which comprises, as represented by mole percentage based on the following oxides, from 56 to 69% of SiO2, from 8 to 16% of Al2O3, from 9 to 22% of Na2O, from 0 to 1% of K2O, from 5.5 to 14% of MgO, from 0 to 2% of ZrO2, and from 0 to 6% of B2O3.Type: ApplicationFiled: March 9, 2017Publication date: June 29, 2017Applicant: ASAHI GLASS COMPANY, LIMITEDInventors: Shusaku Akiba, Shigeki Sawamura, Suguru Murayama, Hiroyuki Ohkawa, Yusuke Kobayashi, Kazutaka Ono, Tetsuya Nakashima
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Patent number: 9656906Abstract: To provide chemically tempered glass which is less likely to break even if scratched. Chemically tempered glass, which comprises, as represented by mole percentage based on the following oxides, from 56 to 72% of SiO2, from 8 to 20% of Al2O3, from 9 to 25% of Na2O, from 0 to 2% of K2O, and from 0 to 15% of MgO, and which has a surface compressive stress of at least 900 MPa and an internal tensile stress of at most 30 MPa. Glass for chemical tempering, which comprises, as represented by mole percentage based on the following oxides, from 56 to 69% of SiO2, from 8 to 16% of Al2O3, from 9 to 22% of Na2O, from 0 to 1% of K2O, from 5.5 to 14% of MgO, from 0 to 2% of ZrO2, and from 0 to 6% of B2O3.Type: GrantFiled: April 17, 2014Date of Patent: May 23, 2017Assignee: Asahi Glass Company, LimitedInventors: Shusaku Akiba, Shigeki Sawamura, Suguru Murayama, Hiroyuki Ohkawa, Yusuke Kobayashi, Kazutaka Ono, Tetsuya Nakashima
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Publication number: 20160253977Abstract: A shift register according to the present invention is a shift register in which a plurality of unit circuits are connected in cascade, wherein the unit circuit includes a first output transistor whose current path is connected between an output terminal and a clock terminal to which a first clock signal is provided; a second output transistor whose current path is connected between the output terminal and a predetermined potential node; a setting device which, when a control signal is active, sets a signal level of the output terminal to a predetermined signal level; a first output control device which provides a signal level of the control signal to a control electrode of the first output transistor to turn off the first output transistor when the control signal is active; and a second output control device which turns off the second output transistor when the control signal is active.Type: ApplicationFiled: July 18, 2014Publication date: September 1, 2016Inventors: Hiroyuki OHKAWA, Shige FURUTA, Yuhichiroh MURAKAMI
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Publication number: 20160240159Abstract: A shift register includes a plurality of unit circuits connected in cascade, each of the unit circuits including: a first output transistor having a current path connected between an output terminal and a clock terminal, the clock terminal being configured to be supplied with a first clock signal; a second output transistor having a current path connected between the output terminal and a predetermined potential node; a setting unit configured to set a signal level of the output terminal to a predetermined signal level in a case where a control signal is active; a first output controller configured to turn off the first output transistor in response to the control signal in the case where the control signal is active, supply a control electrode of the first output transistor with an input signal in response to one of a second clock signal in a case where the control signal is inactive; and a second output controller configured to turn off the second output transistor in the case where the control signal is acType: ApplicationFiled: October 8, 2013Publication date: August 18, 2016Inventors: Hiroyuki OHKAWA, Shige FURUTA, Yuhichiroh MURAKAMI
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Patent number: 9390813Abstract: A unit circuit (11) includes: a transistor (T2) having its drain terminal to be supplied with a clock signal (CK) and its source terminal connected to an output terminal (OUT); a transistor (T9) which, when supplied with an active all-on control signal (AON), outputs an ON voltage to the output terminal (OUT), and which, when supplied with a nonactive all-on control signal (AONB), stops outputting the ON voltage; a transistor (T1) which supplies the ON voltage to a control terminal of the transistor (T2) in accordance with an input signal (IN); a transistor (T4) which, when supplied with the active all-on control signal (AON), supplies an OFF voltage to a control terminal of the transistor (T2). This makes it possible to provide a shift register of a simple structure that can prevent a malfunction from occurring after all-on operation, and to provide a display device.Type: GrantFiled: August 30, 2011Date of Patent: July 12, 2016Assignee: Sharp Kabushiki KaishaInventors: Hiroyuki Ohkawa, Yasushi Sasaki, Yuhichiroh Murakami, Etsuo Yamamoto