Patents by Inventor Hiroyuki Ohtake
Hiroyuki Ohtake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7869290Abstract: A NAND-type flash memory has a memory cell array having NAND cells, each having memory cells capable of being rewritten electrically, a drain of one memory cell and a source of the other memory cell neighboring in a first direction being connected to each other, each of the NAND cells being arranged in a second direction, a plurality of bit lines, each being provided for each of the NAND cells, a plurality of sense amplifiers, each being provided for each of the bit lines, a plurality of data latch circuits, each being provided for each of the sense amplifiers, each of the data latch circuits temporarily holding data sent to and received from the corresponding sense amplifier, at least one test latch circuit which temporarily holds test data supplied from outside, and a data switching circuit which performs control for supplying at least two among the data latch circuits with data held in the test latch circuit.Type: GrantFiled: December 12, 2008Date of Patent: January 11, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Ohtake
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Publication number: 20090154243Abstract: A NAND-type flash memory has a memory cell array having NAND cells, each having memory cells capable of being rewritten electrically, a drain of one memory cell and a source of the other memory cell neighboring in a first direction being connected to each other, each of the NAND cells being arranged in a second direction, a plurality of bit lines, each being provided for each of the NAND cells, a plurality of sense amplifiers, each being provided for each of the bit lines, a plurality of data latch circuits, each being provided for each of the sense amplifiers, each of the data latch circuits temporarily holding data sent to and received from the corresponding sense amplifier, at least one test latch circuit which temporarily holds test data supplied from outside, and a data switching circuit which performs control for supplying at least two among the data latch circuits with data held in the test latch circuit.Type: ApplicationFiled: December 12, 2008Publication date: June 18, 2009Applicant: Kabushiki Kaisha ToshibaInventor: Hiroyuki Ohtake
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Patent number: 7400531Abstract: A semiconductor integrated circuit device has a page buffer, several memory cells to which data is written in accordance with write data stored in the page buffer, and an accumulating counter. The accumulating counter accumulates and stores a number of program loops spent for data write to several memory cells, and outputs the accumulated and stored number of program loops.Type: GrantFiled: June 16, 2006Date of Patent: July 15, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Ohtake, Hiroyuki Dohmae
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Publication number: 20070002638Abstract: A semiconductor integrated circuit device has a page buffer, several memory cells to which data is written in accordance with write data stored in the page buffer, and an accumulating counter. The accumulating counter accumulates and stores a number of program loops spent for data write to several memory cells, and outputs the accumulated and stored number of program loops.Type: ApplicationFiled: June 16, 2006Publication date: January 4, 2007Inventors: Hiroyuki Ohtake, Hiroyuki Dohmae
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Patent number: 7099182Abstract: A first inverter includes a first load element and a first transistor, which are connected between first and second terminals in series, a first input terminal and a first output terminal. A second inverter includes a second load element and a second transistor, which are connected between third and fourth terminals in series, a second input terminal and a second output terminal. A first transfer transistor selectively and electrically connects the first output terminal and a first bit line. A second transfer transistor selectively and electrically connects the second output terminal and a second bit line. When data are read from the memory cell which comprises the first and second inverters and the first and second transfer transistors, a first potential is applied to the second terminal and a second potential different from the first potential is applied to the fourth terminal.Type: GrantFiled: December 28, 2004Date of Patent: August 29, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Ohtake, Osamu Hirabayashi
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Publication number: 20060098475Abstract: A first inverter includes a first load element and a first transistor, which are connected between first and second terminals in series, a first input terminal and a first output terminal. A second inverter includes a second load element and a second transistor, which are connected between third and fourth terminals in series, a second input terminal and a second output terminal. A first transfer transistor selectively and electrically connects the first output terminal and a first bit line. A second transfer transistor selectively and electrically connects the second output terminal and a second bit line. When data are read from the memory cell which comprises the first and second inverters and the first and second transfer transistors, a first potential is applied to the second terminal and a second potential different from the first potential is applied to the fourth terminal.Type: ApplicationFiled: December 28, 2004Publication date: May 11, 2006Inventors: Hiroyuki Ohtake, Osamu Hirabayashi
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Patent number: 6990040Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.Type: GrantFiled: August 31, 2004Date of Patent: January 24, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Ohshima, Hiroyuki Ohtake, Katsumi Abe
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Publication number: 20050024932Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.Type: ApplicationFiled: August 31, 2004Publication date: February 3, 2005Inventors: Shigeo Ohshima, Hiroyuki Ohtake, Katsumi Abe
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Patent number: 6795370Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.Type: GrantFiled: February 18, 2003Date of Patent: September 21, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Ohshima, Hiroyuki Ohtake, Katsumi Abe
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Patent number: 6708264Abstract: A synchronous memory device includes a prefetch address counter. The address counter is composed of an n number of one-bit counter circuits, an n number of adders to which the output signals of these counters are supplied respectively, and an adder control circuit for controlling each adder. A start address is externally supplied to each of the one-bit counter circuits, which in turn count up. When the addressing mode is the sequential mode and the start address is an odd address, each adder performs addition according to the state of the even control signal outputted from the adder control circuit. With the addition, the address outputted from each one-bit counter circuit is inverted, but otherwise the same signal as the address outputted from each one-bit counter circuit is outputted.Type: GrantFiled: June 14, 2000Date of Patent: March 16, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Katsumi Abe, Hiroyuki Ohtake
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Patent number: 6636445Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.Type: GrantFiled: December 13, 2000Date of Patent: October 21, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Shigeo Ohshima, Hiroyuki Ohtake, Katsumi Abe
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Publication number: 20030123297Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.Type: ApplicationFiled: February 18, 2003Publication date: July 3, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeo Ohshima, Hiroyuki Ohtake, Katsumi Abe
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Patent number: 6507526Abstract: When a write & auto precharge command is input into a chip, signals CPSRX and AUTPL are at “H”. After finishing a column operation, the level of the signal CPSRX shift to “L”. When CPSRX=“L” and AUTPL=“H”, if a signal CSLCK is at “H”, an auto precharge enable signal AUTPE is at “H”. The signal AUTPE is at “H” when the signal CSLCK is at “H”, and does not depend upon the leading edge of an external clock VCLK. Since auto precharge is executed from the time a column select line CSL is activated, the time the potential of a selected word line is shifted to a non-selection level can be kept constant irrespective of the frequency of the external clock.Type: GrantFiled: June 27, 2001Date of Patent: January 14, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Ohtake
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Patent number: 6463007Abstract: A synchronous semiconductor memory device such as SDRAM easy in timing adjustment of column selection and capable of reducing cycle time and access time to be minimum value without reducing access margin is provided. The synchronous semiconductor memory device includes a memory cell array constituted in a matrix form, a command decoder and an address buffer operative in synchronism with the leading end of clock signal, a row decoder for decoding row address to select word line of the memory cell, a column control signal generating circuit for generating a column control signal, and a column decoder for taking thereinto column address taken in by the address buffer by a column address taking-in signal generated from the command decoder in synchronism with the leading end of the clock signal to allow a column select signal line to be active.Type: GrantFiled: August 23, 2001Date of Patent: October 8, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Ohtake, Shigeo Ohshima
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Publication number: 20020001254Abstract: A synchronous semiconductor memory device such as SDRAM easy in timinq adjustment of column selection and capable of reducing cycle time and access time to be minimum value without reducing access margin is provided. The synchronous semiconductor memory device includes a memory cell array constituted in a matrix form, a command decoder and an address buffer operative in synchronism with the leading end of clock signal, a row decoder for decoding row address to select word line of the memory cell, a column control signal generating circuit for generating a column control signal, and a column decoder for taking thereinto column address taken in by the address buffer by a column address taking-in signal generated from the command decoder in synchronism with the leading end of the clock signal to allow a column select signal line to be active.Type: ApplicationFiled: August 23, 2001Publication date: January 3, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki Ohtake, Shigeo Ohshima
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Publication number: 20020001244Abstract: When a write & auto precharge command is input into a chip, signals CPSRX and AUTPL are at “H”. After finishing a column operation, the level of the signal CPSRX shift to “L”. When CPSRX=“L” and AUTPL=“H”, if a signal CSLCK is at “H”, an auto precharge enable signal AUTPE is at “H”. The signal AUTPE is at “H” when the signal CSLCK is at “H”, and does not depend upon the leading edge of an external clock VCLK. Since auto precharge is executed from the time a column select line CSL is activated, the time the potential of a selected word line is shifted to a non-selection level can be kept constant irrespective of the frequency of the external clock.Type: ApplicationFiled: June 27, 2001Publication date: January 3, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki Ohtake
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Patent number: 6292412Abstract: A clock synchronous circuit comprising a clock receiver, a delay monitor, a forward pulse delay circuit, a backward pulse delay circuit, a driver, a state-holding section, a control signal generating circuit, a first AND circuit, and a second AND circuit. The delay monitor delays the output of the clock receiver. The forward pulse delay circuit delays the output of the delay monitor. The backward pulse delay circuit delays the output of the clock receiver. The driver receives the output of the backward pulse delay circuit and outputs an internal clock signal. The state-holding section controls the backward pulse delay circuit. The control pulse generating circuit initializes the forward pulse delay circuit. The first AND circuit is provided for controlling the supply of the output of the clock receiver to the delay monitor. The second AND is provided for controlling the supply of the output of the delay monitor to the forward pulse delay circuit.Type: GrantFiled: June 30, 2000Date of Patent: September 18, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Koji Kato, Masahiro Kamoshida, Shigeo Ohshima, Hiroyuki Ohtake
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Patent number: 6292430Abstract: A synchronous semiconductor memory device such as SDRAM easy in timing adjustment of column selection and capable of reducing cycle time and access time to be minimum value without reducing access margin is provided. The synchronous semiconductor memory device includes a memory cell array constituted in a matrix form, a command decoder and an address buffer operative in synchronism with the leading end of clock signal, a row decoder for decoding row address to select word line of the memory cell, a column control signal generating circuit for generating a column control signal, and a column decoder for taking thereinto column address taken in by the address buffer by a column address taking-in signal generated from the command decoder in synchronism with the leading end of the clock signal to allow a column select signal line to be active.Type: GrantFiled: March 15, 2000Date of Patent: September 18, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Ohtake, Shigeo Ohshima
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Publication number: 20010005012Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.Type: ApplicationFiled: December 13, 2000Publication date: June 28, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeo Ohshima, Hiroyuki Ohtake, Katsumi Abe
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Patent number: 6088290Abstract: When a clock enable signal asynchronous with a clock signal is set at a high level, a power-down control circuit sets a power-down signal at a high level to release a power-down mode. When the power-down mode is released, a clock control circuit outputs an internal clock signal such that an output signal of a command decoder can be latched. According to such a constitution, a period of time from the latching of the command after releasing the power-down mode to the time when the command can be transferred will be reduced, and a high-speed operation can be attained.Type: GrantFiled: August 11, 1998Date of Patent: July 11, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Ohtake, Shigeo Ohshima, Takehiro Hasegawa