Patents by Inventor Hiroyuki Ohtake

Hiroyuki Ohtake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10745832
    Abstract: A material shape simulation apparatus for simulating deformation of a three-dimensional woven fiber material is provided and includes: an orientation vector field generation unit generating a model shape orientation vector field on three-dimensional meshes of a model shape of a three-dimensional woven fiber material obtained by stacking sheets of two-dimensional woven fabric made of X-yarn and Y-yarn and binding them with Z-yarn; a parameterization unit that searches for a gradient vector for calculating a material shape orientation vector field, being an orientation vector field of a material shape before deformation of the model shape, from the model shape orientation vector field; and an orientation vector updating unit that updates the model shape orientation vector field by applying a condition of preserving a volume between the model shape orientation vector field and the material shape orientation vector field and a condition that neither the X-yarn nor the Y-yarn expands or contracts.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: August 18, 2020
    Assignees: IHI CORPORATION, The University of Tokyo
    Inventors: Hiroyuki Hishida, Koichi Inagaki, Takeshi Nakamura, Fumiaki Watanabe, Kotaro Morioka, Yutaka Ohtake, Hiromasa Suzuki, Yukie Nagai
  • Patent number: 10650173
    Abstract: A design support apparatus supporting designing of a product which uses a fiber material includes a processor that creates a predicted shape model by predicting a shape of the product before a deformation processing. The processor: creates a 3-dimensional shape model of the product; creates curved shape models by separating the 3-dimensional shape model into two or more fiber layers; sets a correspondence relationship between the curved shape models; creates an orientation vector field in the curved shape models; and predicts the shape of the product before the deformation processing by developing the curved shape models on a flat surface based on the correspondence relationship between the curved shape models and the orientation vector field in the curved shape models, and creates the predicted shape model based on the predicted shape.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: May 12, 2020
    Assignees: IHI CORPORATION, THE UNIVERSITY OF TOKYO
    Inventors: Hiroyuki Hishida, Koichi Inagaki, Takeshi Nakamura, Fumiaki Watanabe, Kotaro Morioka, Yutaka Ohtake, Hiromasa Suzuki, Yukie Nagai
  • Patent number: 10372009
    Abstract: The optical device (100) includes a first substrate (10), a second substrate (20), and an optical layer (30). The first substrate includes a first electrode (11) and a second electrode (12) configured to be provided with mutually different electrical potentials within a pixel. The optical layer may include a medium (31) and a plurality of shape-anisotropic particles (32) dispersed in the medium. At least one of the first electrode and the second electrode may include a plurality of comb teeth portions (11a, 12a) arranged at predetermined intervals along the first direction (D1). When an electric potential difference is applied between the first electrode and the second electrode, the pixel may be configured to have an electrical field distribution in which a strong electric field region having a stronger field intensity than another region is periodically formed parallel to the surface of the optical layer along a second direction (D2) orthogonal to the first direction.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: August 6, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tomoko Teranishi, Hiroyuki Moriwaki, Eiji Satoh, Tadashi Ohtake, Hidefumi Yoshida, Satoshi Matsumura
  • Patent number: 7869290
    Abstract: A NAND-type flash memory has a memory cell array having NAND cells, each having memory cells capable of being rewritten electrically, a drain of one memory cell and a source of the other memory cell neighboring in a first direction being connected to each other, each of the NAND cells being arranged in a second direction, a plurality of bit lines, each being provided for each of the NAND cells, a plurality of sense amplifiers, each being provided for each of the bit lines, a plurality of data latch circuits, each being provided for each of the sense amplifiers, each of the data latch circuits temporarily holding data sent to and received from the corresponding sense amplifier, at least one test latch circuit which temporarily holds test data supplied from outside, and a data switching circuit which performs control for supplying at least two among the data latch circuits with data held in the test latch circuit.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: January 11, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Ohtake
  • Publication number: 20090154243
    Abstract: A NAND-type flash memory has a memory cell array having NAND cells, each having memory cells capable of being rewritten electrically, a drain of one memory cell and a source of the other memory cell neighboring in a first direction being connected to each other, each of the NAND cells being arranged in a second direction, a plurality of bit lines, each being provided for each of the NAND cells, a plurality of sense amplifiers, each being provided for each of the bit lines, a plurality of data latch circuits, each being provided for each of the sense amplifiers, each of the data latch circuits temporarily holding data sent to and received from the corresponding sense amplifier, at least one test latch circuit which temporarily holds test data supplied from outside, and a data switching circuit which performs control for supplying at least two among the data latch circuits with data held in the test latch circuit.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 18, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Ohtake
  • Patent number: 7400531
    Abstract: A semiconductor integrated circuit device has a page buffer, several memory cells to which data is written in accordance with write data stored in the page buffer, and an accumulating counter. The accumulating counter accumulates and stores a number of program loops spent for data write to several memory cells, and outputs the accumulated and stored number of program loops.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: July 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Ohtake, Hiroyuki Dohmae
  • Publication number: 20070002638
    Abstract: A semiconductor integrated circuit device has a page buffer, several memory cells to which data is written in accordance with write data stored in the page buffer, and an accumulating counter. The accumulating counter accumulates and stores a number of program loops spent for data write to several memory cells, and outputs the accumulated and stored number of program loops.
    Type: Application
    Filed: June 16, 2006
    Publication date: January 4, 2007
    Inventors: Hiroyuki Ohtake, Hiroyuki Dohmae
  • Patent number: 7099182
    Abstract: A first inverter includes a first load element and a first transistor, which are connected between first and second terminals in series, a first input terminal and a first output terminal. A second inverter includes a second load element and a second transistor, which are connected between third and fourth terminals in series, a second input terminal and a second output terminal. A first transfer transistor selectively and electrically connects the first output terminal and a first bit line. A second transfer transistor selectively and electrically connects the second output terminal and a second bit line. When data are read from the memory cell which comprises the first and second inverters and the first and second transfer transistors, a first potential is applied to the second terminal and a second potential different from the first potential is applied to the fourth terminal.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: August 29, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Ohtake, Osamu Hirabayashi
  • Publication number: 20060098475
    Abstract: A first inverter includes a first load element and a first transistor, which are connected between first and second terminals in series, a first input terminal and a first output terminal. A second inverter includes a second load element and a second transistor, which are connected between third and fourth terminals in series, a second input terminal and a second output terminal. A first transfer transistor selectively and electrically connects the first output terminal and a first bit line. A second transfer transistor selectively and electrically connects the second output terminal and a second bit line. When data are read from the memory cell which comprises the first and second inverters and the first and second transfer transistors, a first potential is applied to the second terminal and a second potential different from the first potential is applied to the fourth terminal.
    Type: Application
    Filed: December 28, 2004
    Publication date: May 11, 2006
    Inventors: Hiroyuki Ohtake, Osamu Hirabayashi
  • Patent number: 6990040
    Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: January 24, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeo Ohshima, Hiroyuki Ohtake, Katsumi Abe
  • Publication number: 20050024932
    Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.
    Type: Application
    Filed: August 31, 2004
    Publication date: February 3, 2005
    Inventors: Shigeo Ohshima, Hiroyuki Ohtake, Katsumi Abe
  • Patent number: 6795370
    Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: September 21, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeo Ohshima, Hiroyuki Ohtake, Katsumi Abe
  • Patent number: 6708264
    Abstract: A synchronous memory device includes a prefetch address counter. The address counter is composed of an n number of one-bit counter circuits, an n number of adders to which the output signals of these counters are supplied respectively, and an adder control circuit for controlling each adder. A start address is externally supplied to each of the one-bit counter circuits, which in turn count up. When the addressing mode is the sequential mode and the start address is an odd address, each adder performs addition according to the state of the even control signal outputted from the adder control circuit. With the addition, the address outputted from each one-bit counter circuit is inverted, but otherwise the same signal as the address outputted from each one-bit counter circuit is outputted.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: March 16, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsumi Abe, Hiroyuki Ohtake
  • Patent number: 6636445
    Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: October 21, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeo Ohshima, Hiroyuki Ohtake, Katsumi Abe
  • Publication number: 20030123297
    Abstract: An input data register for latching write data is arranged in a position near a memory cell array of a memory core section. The input data register is arranged on the upstream side of a data path used for writing data into a memory cell. Write data input to a data pin which is arranged in the end position on the downstream side is latched in the input data register via a data input buffer, serial/parallel converting circuit and write data line. Data latched in the input data register is written into a memory cell via a DQ write driver, data line pair, I/O gate and bit line pair in a next write cycle.
    Type: Application
    Filed: February 18, 2003
    Publication date: July 3, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeo Ohshima, Hiroyuki Ohtake, Katsumi Abe
  • Patent number: 6507526
    Abstract: When a write & auto precharge command is input into a chip, signals CPSRX and AUTPL are at “H”. After finishing a column operation, the level of the signal CPSRX shift to “L”. When CPSRX=“L” and AUTPL=“H”, if a signal CSLCK is at “H”, an auto precharge enable signal AUTPE is at “H”. The signal AUTPE is at “H” when the signal CSLCK is at “H”, and does not depend upon the leading edge of an external clock VCLK. Since auto precharge is executed from the time a column select line CSL is activated, the time the potential of a selected word line is shifted to a non-selection level can be kept constant irrespective of the frequency of the external clock.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: January 14, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Ohtake
  • Patent number: 6463007
    Abstract: A synchronous semiconductor memory device such as SDRAM easy in timing adjustment of column selection and capable of reducing cycle time and access time to be minimum value without reducing access margin is provided. The synchronous semiconductor memory device includes a memory cell array constituted in a matrix form, a command decoder and an address buffer operative in synchronism with the leading end of clock signal, a row decoder for decoding row address to select word line of the memory cell, a column control signal generating circuit for generating a column control signal, and a column decoder for taking thereinto column address taken in by the address buffer by a column address taking-in signal generated from the command decoder in synchronism with the leading end of the clock signal to allow a column select signal line to be active.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: October 8, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Ohtake, Shigeo Ohshima
  • Publication number: 20020001244
    Abstract: When a write & auto precharge command is input into a chip, signals CPSRX and AUTPL are at “H”. After finishing a column operation, the level of the signal CPSRX shift to “L”. When CPSRX=“L” and AUTPL=“H”, if a signal CSLCK is at “H”, an auto precharge enable signal AUTPE is at “H”. The signal AUTPE is at “H” when the signal CSLCK is at “H”, and does not depend upon the leading edge of an external clock VCLK. Since auto precharge is executed from the time a column select line CSL is activated, the time the potential of a selected word line is shifted to a non-selection level can be kept constant irrespective of the frequency of the external clock.
    Type: Application
    Filed: June 27, 2001
    Publication date: January 3, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki Ohtake
  • Publication number: 20020001254
    Abstract: A synchronous semiconductor memory device such as SDRAM easy in timinq adjustment of column selection and capable of reducing cycle time and access time to be minimum value without reducing access margin is provided. The synchronous semiconductor memory device includes a memory cell array constituted in a matrix form, a command decoder and an address buffer operative in synchronism with the leading end of clock signal, a row decoder for decoding row address to select word line of the memory cell, a column control signal generating circuit for generating a column control signal, and a column decoder for taking thereinto column address taken in by the address buffer by a column address taking-in signal generated from the command decoder in synchronism with the leading end of the clock signal to allow a column select signal line to be active.
    Type: Application
    Filed: August 23, 2001
    Publication date: January 3, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Ohtake, Shigeo Ohshima
  • Patent number: 6292430
    Abstract: A synchronous semiconductor memory device such as SDRAM easy in timing adjustment of column selection and capable of reducing cycle time and access time to be minimum value without reducing access margin is provided. The synchronous semiconductor memory device includes a memory cell array constituted in a matrix form, a command decoder and an address buffer operative in synchronism with the leading end of clock signal, a row decoder for decoding row address to select word line of the memory cell, a column control signal generating circuit for generating a column control signal, and a column decoder for taking thereinto column address taken in by the address buffer by a column address taking-in signal generated from the command decoder in synchronism with the leading end of the clock signal to allow a column select signal line to be active.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: September 18, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Ohtake, Shigeo Ohshima