Patents by Inventor Hiroyuki Oikawa

Hiroyuki Oikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11937069
    Abstract: An audio system includes: a face data detection unit that detects face data on the basis of input image data; an acoustic coefficient acquisition unit that outputs an acoustic coefficient associated with face data output from the face data detection unit; and an acoustic coefficient application unit that performs, on an audio signal, acoustic processing based on an acoustic coefficient acquired by the acoustic coefficient acquisition unit.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 19, 2024
    Assignee: Sony Corporation
    Inventors: Hiroyuki Honma, Toru Chinen, Yoshiaki Oikawa
  • Patent number: 11862121
    Abstract: A liquid crystal apparatus includes a liquid crystal layer, a pixel electrode provided in a display region and configured to be supplied with an image signal at a first frequency, and a first electrode provided in a region outside the display region and configured to be alternately supplied with a positive polarity potential with a potential higher than a predetermined potential and a negative polarity potential with a potential lower than the predetermined potential at a second frequency lower than the first frequency such that a positive polarity period in which the positive polarity potential is supplied and a negative polarity period in which the negative polarity potential is supplied have a same length.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: January 2, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Ken Shimada, Hiroyuki Oikawa, Kiyoshi Hara
  • Publication number: 20230319242
    Abstract: An electro-optical device includes a substrate, a pixel electrode, a transistor disposed in a layer between the pixel electrode and the substrate, a gate relay electrode disposed in a layer between the pixel electrode and the transistor, and a light blocking shield layer disposed in a layer between the gate relay electrode and the transistor. The gate relay electrode is electrically coupled to a gate electrode of the transistor, and includes an opening portion at a position overlapping, at least in plan view, a gap formed between the gate electrode and the light blocking shield layer in plan view.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 5, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki OIKAWA
  • Patent number: 11682361
    Abstract: In a liquid crystal device, an electrode is provided between a pixel area of a first substrate and a seal material, and an AC signal is applied to the electrode where a potential with respect to a common potential applied to a common electrode as a reference potential is alternately switched between a positive polarity and a negative polarity. For the AC signal, a length of a positive polarity period where a polarity becomes positive with respect to the common potential and a length of a negative polarity period where a polarity becomes negative with respect to the common potential are different. When anionic impurities of a liquid crystal layer are focused, a positive polarity period length is greater than a negative polarity period length. When cationic impurities of the liquid crystal layer are focused, a negative polarity period length is greater than a positive polarity period length.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: June 20, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki Oikawa
  • Patent number: 11664387
    Abstract: In an electro-optical device, a first opening and a second opening are provided in an interlayer insulating layer provided in a layer between a transistor and a scanning line, with a semiconductor layer interposed between the first opening and the second opening in plan view. A portion of a gate electrode is provided inside the first opening, and the gate electrode is electrically connected to the scanning line via the first opening. The second opening does not overlap with the gate electrode, and a portion of a first capacitance electrode of a capacitance element is provided in the second opening, the first capacitance electrode having light shielding properties. Therefore, the width of the scanning line can be made narrower than in a case in which the gate electrode and the scanning line are electrically connected to each other via both the first opening and the second opening.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: May 30, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki Oikawa
  • Patent number: 11662640
    Abstract: In an electro-optical device, a transistor includes a semiconductor layer extending in a second direction so as to overlap with a scanning line in plan view. A second contact hole for electrically connecting the scanning line with a gate electrode of the transistor is provided in a second interlayer insulating layer provided in a layer between the scanning line and the transistor. The second contact hole includes a first hole portion extending along the second direction on both sides of the semiconductor layer in plan view, and a second hole portion protruding from the first hole portion toward the semiconductor layer and extending along a first direction.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: May 30, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki Oikawa
  • Patent number: 11636817
    Abstract: In a liquid crystal device, a first pixel area is provided in a pixel area of a first substrate, and a second pixel area is provided between the first pixel area and a seal material. The first pixel area has a first pixel electrode to which an image signal is applied, the image signal having a potential alternately switching between a positive polarity and a negative polarity with reference to a first central potential. The second pixel area includes a second pixel electrode to which a first driving potential is applied, the first driving potential having a potential alternately switching between a positive polarity and a negative polarity with reference to a second central potential, the first central potential and the second central potential having a potential difference set therebetween. Therefore, ionic impurities can be efficiently swept from the first pixel area to the second pixel area.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: April 25, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hiroyuki Oikawa, Masahito Yoshii, Shinta Misawa, Masakazu Nishida
  • Publication number: 20230029855
    Abstract: A liquid crystal apparatus includes a liquid crystal layer, a pixel electrode provided in a display region and configured to be supplied with an image signal at a first frequency, and a first electrode provided in a region outside the display region and configured to be alternately supplied with a positive polarity potential with a potential higher than a predetermined potential and a negative polarity potential with a potential lower than the predetermined potential at a second frequency lower than the first frequency such that a positive polarity period in which the positive polarity potential is supplied and a negative polarity period in which the negative polarity potential is supplied have a same length.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 2, 2023
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Ken SHIMADA, Hiroyuki OIKAWA, Kiyoshi HARA
  • Publication number: 20220383831
    Abstract: In a liquid crystal device, a first pixel area is provided in a pixel area of a first substrate, and a second pixel area is provided between the first pixel area and a seal material. The first pixel area has a first pixel electrode to which an image signal is applied, the image signal having a potential alternately switching between a positive polarity and a negative polarity with reference to a first central potential. The second pixel area includes a second pixel electrode to which a first driving potential is applied, the first driving potential having a potential alternately switching between a positive polarity and a negative polarity with reference to a second central potential, the first central potential and the second central potential having a potential difference set therebetween. Therefore, ionic impurities can be efficiently swept from the first pixel area to the second pixel area.
    Type: Application
    Filed: May 25, 2022
    Publication date: December 1, 2022
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroyuki OIKAWA, Masahito YOSHII, Shinta MISAWA, Masakazu NISHIDA
  • Publication number: 20220375421
    Abstract: In a liquid crystal device, an electrode is provided between a pixel area of a first substrate and a seal material, and an AC signal is applied to the electrode where a potential with respect to a common potential applied to a common electrode as a reference potential is alternately switched between a positive polarity and a negative polarity. For the AC signal, a length of a positive polarity period where a polarity becomes positive with respect to the common potential and a length of a negative polarity period where a polarity becomes negative with respect to the common potential are different. When anionic impurities of a liquid crystal layer are focused, a positive polarity period length is greater than a negative polarity period length. When cationic impurities of the liquid crystal layer are focused, a negative polarity period length is greater than a positive polarity period length.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 24, 2022
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki OIKAWA
  • Patent number: 11424274
    Abstract: In an electro-optical device, in an interlayer insulating layer provided in a layer between a transistor and a scanning line, a first opening and a second opening are respectively provided on both sides of a semiconductor layer in plan view, and a portion of a gate electrode is provided inside each of the first opening and the second opening. Therefore, the gate electrode configures a light shielding wall inside each of the first opening and the second opening. Of the first opening and the second opening, the first opening is provided at a position overlapping with the scanning line in plan view, and the gate electrode is electrically connected to the scanning line via the first opening. The second opening is provided at a position that does not overlap with the scanning line in plan view. Thus, the width of the scanning line can be made narrower.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: August 23, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki Oikawa
  • Publication number: 20210240024
    Abstract: In an electro-optical device, a transistor includes a semiconductor layer extending in a second direction so as to overlap with a scanning line in plan view. A second contact hole for electrically connecting the scanning line with a gate electrode of the transistor is provided in a second interlayer insulating layer provided in a layer between the scanning line and the transistor. The second contact hole includes a first hole portion extending along the second direction on both sides of the semiconductor layer in plan view, and a second hole portion protruding from the first hole portion toward the semiconductor layer and extending along a first direction.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 5, 2021
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki OIKAWA
  • Publication number: 20210242246
    Abstract: In an electro-optical device, in an interlayer insulating layer provided in a layer between a transistor and a scanning line, a first opening and a second opening are respectively provided on both sides of a semiconductor layer in plan view, and a portion of a gate electrode is provided inside each of the first opening and the second opening. Therefore, the gate electrode configures a light shielding wall inside each of the first opening and the second opening. Of the first opening and the second opening, the first opening is provided at a position overlapping with the scanning line in plan view, and the gate electrode is electrically connected to the scanning line via the first opening. The second opening is provided at a position that does not overlap with the scanning line in plan view. Thus, the width of the scanning line can be made narrower.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 5, 2021
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki OIKAWA
  • Publication number: 20210242245
    Abstract: In an electro-optical device, a first opening and a second opening are provided in an interlayer insulating layer provided in a layer between a transistor and a scanning line, with a semiconductor layer interposed between the first opening and the second opening in plan view. A portion of a gate electrode is provided inside the first opening, and the gate electrode is electrically connected to the scanning line via the first opening. The second opening does not overlap with the gate electrode, and a portion of a first capacitance electrode of a capacitance element is provided in the second opening, the first capacitance electrode having light shielding properties. Therefore, the width of the scanning line can be made narrower than in a case in which the gate electrode and the scanning line are electrically connected to each other via both the first opening and the second opening.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 5, 2021
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki OIKAWA
  • Patent number: 10859882
    Abstract: A liquid crystal apparatus as an electro-optical device includes a TFT including a semiconductor layer and a gate electrode, a scan line electrically connected to the gate electrode and provided in a layer different from a layer where the gate electrode is provided, a capacitance line, and a conductive light shielding film electrically connected to the capacitance line. The light shielding film is provided in a layer between the gate electrode and the scan line, and in a plan view, overlaps with at least a part of a low-concentration drain region of the semiconductor layer.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: December 8, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Toru Nimura, Hiroyuki Oikawa, Shinsuke Fujikawa
  • Publication number: 20200312890
    Abstract: In the electro-optical device, a gate electrode and a scanning line are electrically connected through a first contact hole disposed on the first insulating layer (interlayer insulating layer) overlapping the transistor. In a layer between the gate electrode and the scanning line, a first light shielding layer to which a constant potential is applied is disposed, and a light shielding portion electrically connected to the first light shielding layer covers a part of the semiconductor layer from both sides in a width direction. The light shielding portion includes a first portion that electrically connects the second light shielding layer and the first light shielding layer, and a second portion protruding from the first portion toward the semiconductor layer.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 1, 2020
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroyuki OIKAWA, Toru NIMURA, Shinsuke FUJIKAWA
  • Patent number: 10620494
    Abstract: In an element substrate of an electro-optical device, a semiconductor layer of a transistor has an L shape bending to overlap with both a scanning line and a data line. A first light shielding layer overlaps with a lower layer side of the semiconductor layer. A first light shielding wall and a second light shielding wall are provided on both sides of a semiconductor layer portion between a channel region and a second source/drain region (drain region) of the semiconductor layer. The first light shielding wall and the second light shielding wall to which a constant potential is applied prevent the semiconductor layer portion from being electrically affected even when the first light shielding wall and the second light shielding wall come close to the semiconductor layer portion.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: April 14, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Hiroyuki Oikawa, Toru Nimura, Shinsuke Fujikawa
  • Patent number: 10495873
    Abstract: An electronic device includes an electro-optical device including a substrate, a mirror for optical modulation disposed above one surface side of the substrate, and electrodes including an elevated address electrode disposed between the mirror and the substrate. The light source emits light toward the mirror in a direction at an angle with respect to the direction perpendicular to the mirror. The mirror includes a first incident end face which is an end face of the mirror located at a side from which the light is radiated, and a first antireflection film is provided on the first incident end face. The elevated address electrode includes a second incident end face which is an end face of the elevated address electrode located at the side from which the light is radiated, and a second antireflection film is provided on the second incident end face.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 3, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki Oikawa
  • Publication number: 20190331972
    Abstract: A liquid crystal apparatus as an electro-optical device includes a TFT including a semiconductor layer and a gate electrode, a scan line electrically connected to the gate electrode and provided in a layer different from a layer where the gate electrode is provided, a capacitance line, and a conductive light shielding film electrically connected to the capacitance line. The light shielding film is provided in a layer between the gate electrode and the scan line, and in a plan view, overlaps with at least a part of a low-concentration drain region of the semiconductor layer.
    Type: Application
    Filed: April 24, 2019
    Publication date: October 31, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Toru NIMURA, Hiroyuki OIKAWA, Shinsuke FUJIKAWA
  • Patent number: 10402296
    Abstract: A data collection apparatus includes a data collection section configured to receive sequential time-series output data pieces for each of data sources, a data shaping section configured to perform data shaping processing on the sequential time-series output data pieces based on a predetermined data shaping rule set for each of the data sources such that the resulting data pieces are reduced in number or in data amount as compared with the output data pieces output from the data source, a data transmission section configured to transmit the output data pieces to the monitor control apparatus, and a data shaping rule control section configured to receive the data shaping rule set for each of the data sources from the monitor control apparatus and to set the received data shaping rule in the data shaping section.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: September 3, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA SOLUTIONS CORPORATION
    Inventors: Kazuaki Takahashi, Takehiro Yoshimoto, Nobuyuki Fukushima, Masumi Inaba, Hiroyuki Oikawa