Patents by Inventor Hiroyuki Okino

Hiroyuki Okino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11932263
    Abstract: A travel sickness estimation system includes an estimation unit and an output unit. The estimation unit is configured to perform estimation processing of estimating, based on person information indicating conditions of a person who is on board a moving vehicle, whether or not the person is in circumstances that would cause travel sickness for him or her. The output unit is configured to output a result of the estimation processing performed by the estimation unit.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: March 19, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuta Moriura, Yoshitaka Nakamura, Yasufumi Kawai, Hiroyuki Handa, Yohei Morishita, Toru Okino, Hiroyuki Hagino, Toru Sakuragawa, Satoshi Morishita
  • Publication number: 20240046417
    Abstract: An image processing device for removing a noise having directionality in a first direction from an image containing the noise without affecting information on minute shading of luminance of the image, including: a high-pass filter unit configured to perform filtering processing on an image containing a noise having directionality in a horizontal direction with a high-pass filter in the horizontal direction; a low-pass filter unit configured to perform filtering processing on the image in a vertical direction with a low-pass filter; and an addition unit configured to add an image processed by the high-pass filter unit and an image processed by the low-pass filter unit.
    Type: Application
    Filed: September 3, 2021
    Publication date: February 8, 2024
    Inventors: Kumiko KONISHI, Akio YONEYAMA, Hiroyuki OKINO
  • Publication number: 20230084128
    Abstract: In a silicon carbide substrate including: a SiC substrate; and a first semiconductor layer, a second semiconductor layer and a drift layer that are epitaxial layers sequentially formed on the SiC substrate, an impurity concentration of the first semiconductor layer is lower than impurity concentrations of the SiC substrate and the second semiconductor layer, and the second semiconductor layer is formed to have a high impurity concentration or a large thickness.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 16, 2023
    Inventors: Kumiko KONISHI, Hiroyuki OKINO, Taisuke HIROOKA
  • Publication number: 20180047855
    Abstract: In a Schottky barrier diode comprising silicon carbide: an active region includes a first semiconductor region of a first conductivity type configuring a first Schottky junction having a plurality of linear patterns between a first electrode and the first semiconductor region and a second semiconductor region of a second conductivity type adjacent to the first Schottky junction and connected to the first electrode; at the border of the active region and a periphery region, a second Schottky junction comprising the first electrode and the first semiconductor region and having at least one annular pattern surrounding the linear patterns is provided and the second semiconductor region is adjacent to the second Schottky junction and is connected to the first electrode; and the first and second Schottky junctions are conductive parts and the second semiconductor region is a nonconductive part in a forward bias state.
    Type: Application
    Filed: May 15, 2015
    Publication date: February 15, 2018
    Inventors: Kan YASUI, Hiroyuki MATSUSHIMA, Hiroyuki OKINO
  • Patent number: 9508611
    Abstract: In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 29, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinobu Kimura, Natsuki Tsuno, Hiroya Ohta, Renichi Yamada, Hirotaka Hamamura, Toshiyuki Ohno, Hiroyuki Okino, Yuki Mori
  • Publication number: 20160190020
    Abstract: In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance.
    Type: Application
    Filed: August 14, 2013
    Publication date: June 30, 2016
    Inventors: Yoshinobu KIMURA, Natsuki TSUNO, Hiroya OHTA, Renichi YAMADA, Hirotaka HAMAMURA, Toshiyuki OHNO, Hiroyuki OKINO, Yuki MORI
  • Patent number: 9117836
    Abstract: A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: August 25, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Tega, Yasuhiro Shimamoto, Yuki Mori, Hirotaka Hamamura, Hiroyuki Okino, Digh Hisamoto
  • Patent number: 9000448
    Abstract: A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: April 7, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Hirotaka Hamamura, Yasuhiro Shimamoto, Hiroyuki Okino
  • Publication number: 20130234163
    Abstract: A MOSFET having a high mobility may be obtained by introducing nitrogen to the channel region or the interface between the gate dielectric film and the SiC substrate of the SiC MOSFET, but there is a problem that a normally-on MOSFET is obtained. For realizing both a high mobility and normally-off, and for providing a SiC MOSFET having further high reliability, nitrogen is introduced to the channel region of the SiC substrate or the interface between the gate dielectric film and the SiC substrate, and furthermore a metal oxide film having a thickness of 10%, or less of the total thickness of the gate dielectric film is inserted in the gate dielectric film.
    Type: Application
    Filed: March 29, 2011
    Publication date: September 12, 2013
    Inventors: Hirotaka Hamamura, Yasuhiro Shimamoto, Hiroyuki Okino
  • Publication number: 20120217513
    Abstract: A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.
    Type: Application
    Filed: January 12, 2012
    Publication date: August 30, 2012
    Inventors: Naoki TEGA, Yasuhiro Shimamoto, Yuki Mori, Hirotaka Hamamura, Hiroyuki Okino, Digh Hisamoto