Patents by Inventor Hiroyuki Onoda
Hiroyuki Onoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230033323Abstract: There is provided a plasma source comprising a first chamber configured to form a flat first plasma generation space, and having a first wall and a second wall, a gas supply configured to supply gas into the first chamber, an electromagnetic wave supply having a dielectric window that is provided in an opening provided in the first wall to face the first plasma generation space, and configured to supply an electromagnetic wave through the dielectric window into the first chamber. The plasma source comprises a plasma supply configured to supply radicals contained in plasma that is generated from the gas supplied into the first chamber by the electromagnetic wave to an outside of the first chamber, and a plasma ignition source provided in the first chamber to protrude from an inner wall of the second wall facing the dielectric window and to be separated from the dielectric window.Type: ApplicationFiled: July 20, 2022Publication date: February 2, 2023Inventors: Taro IKEDA, Yuki OSADA, Hiroyuki MIYASHITA, Hiroyuki ONODA, Satoru KAWAKAMI
-
Publication number: 20220411920Abstract: The present disclosure provides a substrate processing method and a substrate processing apparatus that perform selective film formation. The substrate processing method includes: forming a silicon-containing film by repeating forming an adsorption layer on a substrate on which a pattern of a concave portion is formed by supplying a silicon-containing gas to the substrate and generating plasma of a reaction gas to cause the plasma to react with the adsorption layer; and etching the silicon-containing film, wherein the forming the silicon-containing film includes modifying at least one of the adsorption layer and the silicon-containing film by generating a He-containing plasma.Type: ApplicationFiled: November 10, 2020Publication date: December 29, 2022Inventors: Munehito KAGAYA, Tadashi MITSUNARI, Hiroyuki ONODA
-
Publication number: 20220165544Abstract: There is provided a plasma processing device.Type: ApplicationFiled: March 13, 2020Publication date: May 26, 2022Inventors: Munehito KAGAYA, Satoru KAWAKAMI, Tsuyoshi MORIYA, Tatsuo MATSUDO, Jun YAMAWAKU, Hiroyuki ONODA
-
Publication number: 20150369322Abstract: This Si-killed steel wire rod has Si-killed steel which contains specific chemical components that contain, as 80% or more of the number of inclusions, specific CaO—Al2O3—SiO2 inclusions, wherein the average composition of the MnO—Al2O3—SiO2 inclusions that satisfies the following (3A) satisfies the following (3B). (3A) If CaO+Al2O3+SiO2+MgO+MnO serves as the 100% standard, MnO+Al2O3+SiO2?80%, MnO>CaO. (3B) When CaO+Al2O3+SiO2+MgO+MnO serves as the 100% standard, MnO: 10 to 70%, Al2O3: 3 to 50%, SiO2: 20 to 75%.Type: ApplicationFiled: January 15, 2014Publication date: December 24, 2015Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.)Inventors: Tomoko SUGIMURA, Hiroaki SAKAI, Yasumasa YOSHIDA, Hirofumi TAI, Hiroki OHTA, Hiroyuki ONODA
-
Publication number: 20140252491Abstract: According to one embodiment, a semiconductor device includes a first epitaxial layer of a first material, a second epitaxial layer of a second material, a conductive material, a third epitaxial layer of the first material and a fourth epitaxial layer of the second material. The first epitaxial layer is formed in the source region and the drain region of a P-MOS transistor. The second epitaxial layer is formed in the source region and the drain region of an n-MOS transistor. The conductive material includes a gate electrode structure. The third epitaxial layer and the fourth epitaxial layer are laminated around the polysilicon.Type: ApplicationFiled: March 5, 2013Publication date: September 11, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki ONODA
-
Publication number: 20120228628Abstract: A semiconductor device and methods of fabricating semiconductor devices are provided. A method involves forming a semiconductor substrate on a source region and a drain region, the semiconductor substrate comprises a first crystal. The method also involves forming an epitaxial layer of a second crystal on the semiconductor substrate. The first crystal has a first lattice constant and the second crystal has a second lattice constant. The first epitaxial layer does not touch a spacer or a gate electrode. Forming the epitaxial layer can comprise forming a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer has a conductivity type impurity that is less than the conductivity type impurity of the second epitaxial layer.Type: ApplicationFiled: March 7, 2011Publication date: September 13, 2012Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Hiroyuki Onoda, Hiroyuki Oota
-
Patent number: 7909698Abstract: With a game system, a timing fetch section fetches an input-timing for input data determined to be valid by an input-determination section, and an evaluation section compares the fetched input-timing and a reference-timing, and evaluates an operation with an operation section by a player or a sound-input action performed in answer to a first or second direction-mark. An input-reception section receives first and second input data generated based on an operation-detection of the operation section a sound-detection of the sound-detection section, respectively, and an input-determination section compares the first and second input data, determines that the first input data is valid when it is determined that the operation with the operation section by the player and the sound-input action by the player overlap within a given period, based on the first and second input data, and determines that the first and second input data are valid in other cases.Type: GrantFiled: September 9, 2004Date of Patent: March 22, 2011Assignees: Namco Bandai Games, Inc., Nintendo Co., Ltd.Inventors: Hiroyuki Onoda, Hiroumi Endo, Hiroshi Igarashi, Junji Takamoto, Takeshi Nagareda, Kuniaki Ito, Takao Shimizu
-
Patent number: 7910445Abstract: A method of fabricating a semiconductor device according to one embodiment of the invention includes: forming a gate electrode on a semiconductor substrate through a gate insulating film; forming offset spacers on side surfaces of the gate electrode, respectively; etching the semiconductor substrate with a channel region below the offset spacers and the gate electrode being left by using the offset spacers as a mask; forming a first epitaxial layer made of a crystal having a lattice constant different from that of a crystal constituting the semiconductor substrate on the semiconductor substrate thus etched; etching at least a portion of the first epitaxial layer adjacent to the channel region to a predetermined depth from a surface of the first epitaxial layer toward the semiconductor substrate side; and forming a second epitaxial layer containing therein a conductivity type impurity on the first epitaxial layer thus etched.Type: GrantFiled: October 15, 2008Date of Patent: March 22, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Onoda
-
Patent number: 7722450Abstract: A game system including: a music reproduction section which reproduces given music data stored in a storage section; a display control section which performs display control of changing a relative positional relationship among a direction mark which directs an operation to be performed by a player using an operation section, a special direction mark for the second game and a reference mark for timing judgment of the operation in association with a reproduction state of the music data to cause the direction mark and the reference mark to come closer; a timing acquisition section which acquires operation timing when the player operates the operation section for the direction mark; and a game calculation section which performs calculation processing of a first game of comparing the acquired operation timing with timing criteria and calculation processing of a second game differing from the first game based on operation information of the operation section for the special direction mark.Type: GrantFiled: September 9, 2004Date of Patent: May 25, 2010Assignees: Namco Bandai Games Inc., Nintendo Co., Ltd.Inventors: Hiroyuki Onoda, Hiroumi Endo, Hiroshi Igarashi, Junji Takamoto, Takeshi Nagareda
-
Patent number: 7628699Abstract: A game system includes: a direction mark storage section which stores image data of a direction mark that specifies a player's maneuver; a display controller which controls display of a plurality of display objects including the direction mark; a timing fetch section which fetches a maneuver timing; and an evaluation section which evaluates player's performance, based on a result of comparison between the fetched maneuver timing and a reference timing. The display controller displays the direction mark to specify a combination of a series of consecutive maneuvers by a single mark. When the player has input a series of consecutive maneuvers in accordance with a direction of the direction mark, the evaluation section compares the timing of the series of consecutive maneuvers with a reference timing, to evaluate the performance of the player.Type: GrantFiled: September 8, 2004Date of Patent: December 8, 2009Assignees: Namco Bandai Games Inc., Nintendo Co., Ltd.Inventors: Hiroyuki Onoda, Hiroumi Endo, Hiroshi Igarashi, Junji Takamoto, Takeshi Nagareda
-
Patent number: 7582015Abstract: A game system includes: a direction mark storage section which stores image data of a direction mark which directs an operation of a player; a display control section which performs display control of a plurality of display objects including the direction mark; a timing acquisition section which acquires an operation timing; and an evaluation section which compares the acquired operation timing with a reference timing and evaluates the operation of the player. The display control section performs control of displaying the direction mark which directs the player to operate a plurality of operation regions by one mark. When the player operates the plurality of the operation regions of the operation section, the evaluation section evaluates the operation of the player by comparing the operation timing for the plurality of operation regions and the reference timing.Type: GrantFiled: September 9, 2004Date of Patent: September 1, 2009Assignees: Namco Bandai Games Inc., Nintendo Co., Ltd.Inventors: Hiroyuki Onoda, Hiroumi Endo, Hiroshi Igarashi, Junji Takamoto, Takeshi Nagareda
-
Publication number: 20090194816Abstract: A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first spacer formed on a side face of the first gate electrode, a first channel region formed in the semiconductor substrate under the first gate insulating film, a first source/drain region formed on both sides of the first channel region and comprising an extension region formed by a conductivity type impurity segregated on the first channel side, and a first silicide layer formed on the first source/drain region so as to contact with the first spacer; a p-type transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second spacer formed on a side face of the second gate electrode, a gate sidewall formed on a side face of the second spacer, a second channel region formed in the semiconductor substrate under the second gate insulating film, a second source/draiType: ApplicationFiled: February 2, 2009Publication date: August 6, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki Onoda
-
Publication number: 20090140302Abstract: A method of fabricating a semiconductor device according to one embodiment of the invention includes: forming a gate electrode on a semiconductor substrate through a gate insulating film; forming offset spacers on side surfaces of the gate electrode, respectively; etching the semiconductor substrate with a channel region below the offset spacers and the gate electrode being left by using the offset spacers as a mask; forming a first epitaxial layer made of a crystal having a lattice constant different from that of a crystal constituting the semiconductor substrate on the semiconductor substrate thus etched; etching at least a portion of the first epitaxial layer adjacent to the channel region to a predetermined depth from a surface of the first epitaxial layer toward the semiconductor substrate side; and forming a second epitaxial layer containing therein a conductivity type impurity on the first epitaxial layer thus etched.Type: ApplicationFiled: October 15, 2008Publication date: June 4, 2009Inventor: Hiroyuki ONODA
-
Publication number: 20050130740Abstract: With a game system, a timing fetch section fetches an input-timing for input data determined to be valid by an input-determination section, and an evaluation section compares the fetched input-timing and a reference-timing, and evaluates an operation with an operation section by a player or a sound-input action performed in answer to a first or second direction-mark. An input-reception section receives first and second input data generated based on an operation-detection of the operation section a sound-detection of the sound-detection section, respectively, and an input-determination section compares the first and second input data, determines that the first input data is valid when it is determined that the operation with the operation section by the player and the sound-input action by the player overlap within a given period, based on the first and second input data, and determines that the first and second input data are valid in other cases.Type: ApplicationFiled: September 9, 2004Publication date: June 16, 2005Applicants: NAMCO LTD., NINTENDO CO., LTD.Inventors: Hiroyuki Onoda, Hiroumi Endo, Hiroshi Igarashi, Junji Takamoto, Takeshi Nagareda, Kuniaki Ito, Takao Shimizu
-
Patent number: 6894124Abstract: This invention provides high solid paint compositions comprising as the basic components a hydroxyl-containing compound having a weight-average molecular weight of not more than 1,000 and a hydroxyl value of 200-800 mgKOH/g, and a polyisocyanate compound, and a process for forming multi-layered coating film using any of said compositions.Type: GrantFiled: October 31, 2001Date of Patent: May 17, 2005Assignee: Kansai Paint Co., Ltd.Inventors: Yoshizumi Matsuno, Hiroyuki Onoda, Takashi Noguchi, Hisashi Isaka
-
Publication number: 20050101364Abstract: A game system includes: a direction mark storage section which stores image data of a direction mark that specifies a player's maneuver; a display controller which controls display of a plurality of display objects including the direction mark; a timing fetch section which fetches a maneuver timing; and an evaluation section which evaluates player's performance, based on a result of comparison between the fetched maneuver timing and a reference timing. The display controller displays the direction mark to specify a combination of a series of consecutive maneuvers by a single mark. When the player has input a series of consecutive maneuvers in accordance with a direction of the direction mark, the evaluation section compares the timing of the series of consecutive maneuvers with a reference timing, to evaluate the performance of the player.Type: ApplicationFiled: September 8, 2004Publication date: May 12, 2005Applicants: NAMCO LTD., NINTENDO CO., LTD.Inventors: Hiroyuki Onoda, Hiroumi Endo, Hiroshi Igarashi, Junji Takamoto, Takeshi Nagareda
-
Publication number: 20050085284Abstract: A game system including: a music reproduction section which reproduces given music data stored in a storage section; a display control section which performs display control of changing a relative positional relationship among a direction mark which directs an operation to be performed by a player using an operation section, a special direction mark for the second game and a reference mark for timing judgment of the operation in association with a reproduction state of the music data to cause the direction mark and the reference mark to come closer; a timing acquisition section which acquires operation timing when the player operates the operation section for the direction mark; and a game calculation section which performs calculation processing of a first game of comparing the acquired operation timing with timing criteria and calculation processing of a second game differing from the first game based on operation information of the operation section for the special direction mark.Type: ApplicationFiled: September 9, 2004Publication date: April 21, 2005Applicants: NAMCO LTD., NINTENDO CO., LTD.Inventors: Hiroyuki Onoda, Hiroumi Endo, Hiroshi Igarashi, Junji Takamoto, Takeshi Nagareda
-
Publication number: 20050085297Abstract: A game system includes: a direction mark storage section which stores image data of a direction mark which directs an operation of a player; a display control section which performs display control of a plurality of display objects including the direction mark; a timing acquisition section which acquires an operation timing; and an evaluation section which compares the acquired operation timing with a reference timing and evaluates the operation of the player. The display control section performs control of displaying the direction mark which directs the player to operate a plurality of operation regions by one mark. When the player operates the plurality of the operation regions of the operation section, the evaluation section evaluates the operation of the player by comparing the operation timing for the plurality of operation regions and the reference timing.Type: ApplicationFiled: September 9, 2004Publication date: April 21, 2005Applicants: NAMCO LTD., NINTENDO CO., LTD.Inventors: Hiroyuki Onoda, Hiroumi Endo, Hiroshi Igarashi, Junji Takamoto, Takeshi Nagareda
-
Publication number: 20030176568Abstract: This invention relates to a high-solids coating composition which characteristically comprises:Type: ApplicationFiled: March 11, 2003Publication date: September 18, 2003Inventors: Hiroyuki Onoda, Kazutoshi Sugiura, Yoshizumi Matsuno, Hisashi Isaka
-
Publication number: 20020082341Abstract: This invention provides high solid paint compositions comprising as the basic components a hydroxyl-containing compound having a weight-average molecular weight of not more than 1,000 and a hydroxyl value of 200-800 mgKOH/g, and a polyisocyanate compound, and a process for forming multi-layered coating film using any of said compositions.Type: ApplicationFiled: October 31, 2001Publication date: June 27, 2002Inventors: Yoshizumi Matsuno, Hiroyuki Onoda, Takashi Noguchi, Hisashi Isaka