Patents by Inventor Hiroyuki Oonishi

Hiroyuki Oonishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200065057
    Abstract: An aspect of the present invention allows a natural, humanlike conversation to be carried out between electronic apparatus. The audio adjustment device (1) includes: a sound analyzing section (21) for analyzing a second sound outputted from a second electronic apparatus; and an element adjusting section (24) for adjusting a first element characterizing the first sound, the first element being adjusted on a basis of either a content of a text in the second sound or a second element characterizing the second sound, the content of the text in the second sound and the second element being obtained by analysis by the sound analyzing section (21).
    Type: Application
    Filed: August 31, 2017
    Publication date: February 27, 2020
    Inventors: KAZUNORI WAKI, KEI OKUDA, YOSHIKO IMAKI, HIROYUKI OONISHI, FUMITOSHI TANOUE, SATOSHI EGUCHI
  • Patent number: 10566196
    Abstract: A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 ?·cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050° C. and 1200° C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: February 18, 2020
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Osamu Ishikawa, Kenji Meguro, Taishi Wakabayashi, Hiroyuki Oonishi
  • Publication number: 20190130046
    Abstract: The generating device (3, 3a, 3b) includes a control section (20, 20a, 20b) and a communication section (29). The control section obtains data via the communication section (29), which data indicates a content which has been caused to be displayed on a display screen of a terminal device (2, 2a) by an application, and the control section generates a shared page including the content.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 2, 2019
    Inventors: HIROYUKI OONISHI, MOTOKI SONE, TSUYOSHI YAMAGUCHI, HIROAKI KONDO
  • Publication number: 20180122639
    Abstract: A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 ?-cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050° C. and 1200° C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.
    Type: Application
    Filed: March 14, 2016
    Publication date: May 3, 2018
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro KOBAYASHI, Osamu ISHIKAWA, Kenji MEGURO, Taishi WAKABAYASHI, Hiroyuki OONISHI
  • Patent number: 8699236
    Abstract: A conductive buffer material (11) is one surface of a display panel (29) sandwiched between a first member (BZ1) and a second member (CS), and is interposed between a first panel surface facing the metallic first member (BZ1) and the first member (BZ1). The conductive buffer material (11) includes an inclusion material (15) and a conductive envelope material (14) that wraps the inclusion material (15), and the conductive buffer material (11) includes a main portion in which part of the envelope material (14) is brought closer to the first panel surface and the first member (BZ1) by the inclusion material (15) having a given thickness or more.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: April 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kohji Hisakawa, Hiroyuki Oonishi
  • Publication number: 20120063113
    Abstract: A conductive buffer material (11) is one surface of a display panel (29) sandwiched between a first member (BZ1) and a second member (CS), and is interposed between a first panel surface facing the metallic first member (BZ1) and the first member (BZ1). The conductive buffer material (11) includes an inclusion material (15) and a conductive envelope material (14) that wraps the inclusion material (15), and the conductive buffer material (11) includes a main portion in which part of the envelope material (14) is brought closer to the first panel surface and the first member (BZ1) by the inclusion material (15) having a given thickness or more.
    Type: Application
    Filed: March 1, 2010
    Publication date: March 15, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kohji Hisakawa, Hiroyuki Oonishi