Patents by Inventor Hiroyuki Orihara

Hiroyuki Orihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130245975
    Abstract: A drawing device includes a memory and a processor coupled to the memory. The processor executes a process including measuring voltages of planes of layers in a laminated circuit board and drawing the voltages of the planes that are measured on a graph having a voltage set on one axis and having a layer set on the other axis.
    Type: Application
    Filed: December 19, 2012
    Publication date: September 19, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Takashi KOBAYASHI, Mitsunobu OKANO, Shogo FUJIMORI, Hiroyuki ORIHARA
  • Publication number: 20120041748
    Abstract: A design support apparatus includes an extraction part, a creation part, and a correction part. The extraction part extracts from among a power supply layer and a ground layer a range related to a signal transmission of a pair of signal transmission circuit models disposed in a predetermined layer of a substrate model having a plurality of layers. The creation part processes, based on given constrained conditions, the power supply layer and ground layer in a range extracted by the extraction part and creates a layer model. The correction part corrects the substrate model based on the created layer model.
    Type: Application
    Filed: August 11, 2011
    Publication date: February 16, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Hiroyuki Orihara
  • Patent number: 7136797
    Abstract: The apparatus comprises the syntax checking section that checks the syntax of a device model according to a check table showing the relation between the syntax of the device model showing electrical characteristics of a semiconductor device and an amendment when deviating from the syntax. The syntax error amendment creating section corrects the device model according to a corresponding amendment when a description deviating from the syntax is checked by the syntax checking section.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: November 14, 2006
    Assignee: Fujitsu Limited
    Inventors: Masaki Tosaka, Toshio Karino, Tatsuo Koizumi, Jiro Yoneda, Megumi Nagata, Hiroyuki Orihara, Hikoyuki Kawata
  • Patent number: 7035783
    Abstract: In a simulation considering a skin effect, a signal conductor is vertically and horizontally divided by faces parallel to the surface of the signal conductor, which are set so that intervals are smaller as the faces are nearer to the surface, and larger as the faces are farther from the surface. Also a ground conductor is vertically divided with a similar method, and an integration calculation is made, so that the resistance of the signal conductor, which corresponds to a given frequency, is obtained.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: April 25, 2006
    Assignee: Fujitsu LImited
    Inventors: Megumi Nagata, Masaki Tosaka, Kazuhiko Tokuda, Hiroyuki Orihara, Hikoyuki Kawata
  • Publication number: 20030083853
    Abstract: In a simulation considering a skin effect, a signal conductor is vertically and horizontally divided by faces parallel to the surface of the signal conductor, which are set so that intervals are smaller as the faces are nearer to the surface, and larger as the faces are farther from the surface. Also a ground conductor is vertically divided with a similar method, and an integration calculation is made, so that the resistance of the signal conductor, which corresponds to a given frequency, is obtained.
    Type: Application
    Filed: January 23, 2002
    Publication date: May 1, 2003
    Applicant: Fujitsu Limited
    Inventors: Megumi Nagata, Masaki Tosaka, Kazuhiko Tokuda, Hiroyuki Orihara, Hikoyuki Kawata
  • Publication number: 20020156607
    Abstract: The apparatus comprises the syntax checking section that checks the syntax of a device model according to a check table showing the relation between the syntax of the device model showing electrical characteristics of a semiconductor device and an amendment when deviating from the syntax. The syntax error amendment creating section corrects the device model according to a corresponding amendment when a description deviating from the syntax is checked by the syntax checking section.
    Type: Application
    Filed: July 19, 2001
    Publication date: October 24, 2002
    Applicant: Fujitsu Limited
    Inventors: Masaki Tosaka, Toshio Karino, Tatsuo Koizumi, Jiro Yoneda, Megumi Nagata, Hiroyuki Orihara, Hikoyuki Kawata
  • Patent number: 5790414
    Abstract: An automatic routing method and an automatic routing apparatus enable an optimum automatic routing under severe design conditions due to high-density mounting of an object of a wiring design such as an LSI, a multichip module, a printed wiring board, etc. The automatic routing apparatus has an area input unit for inputting area information for setting a routing controlled area in which an automatic routing is performed under specific routing control conditions within a wiring area of an object of the wiring design, a condition input unit for inputting condition information for designating the routing control conditions in the routing controlled area set according to the area information inputted from the area input unit, and an automatic routing unit for automatically routing under the specific routing control conditions designated according to the condition information inputted from the condition input unit within the routing controlled area.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: August 4, 1998
    Assignee: Fujitsu Limited
    Inventors: Mitsunobu Okano, Hiroshi Miura, Toshiyasu Sakata, Hiroyuki Orihara
  • Patent number: 5644500
    Abstract: This invention is directed to a method and apparatus to find out an optimum solution in automatic routing or automatic placement with certainty and at a high-speed to improve a routing rate, and to realize automatic routing in a high-density. To these end, a routing approach is selected in a conversational mode while routing efficiency is consulted to compose routing processing procedure so as to generate a routing program. Besides, component placement processing procedures designated according to placement control information are combined to generate the placement program. A straight line between component pins adjacent to each other is defined as a chord, a wave for maze method routing is generated from a start point toward an end point of a routing path and propagated between the chords adjacent to each other.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: July 1, 1997
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Miura, Masato Ariyama, Kazuyuki Iida, Kazufumi Iwahara, Mitsunobu Okano, Hiroyuki Orihara, Akira Katsumata, Toshiyasu Sakata, Masaharu Nishimura, Hirofumi Hamamura, Naoki Murakami, Mitsuru Yasuda, Yasuhiro Yamashita, Ryouji Yamada, Atsushi Yamane