Abstract: Polyurethane elastomer foams can be prepared by mixing an isocyanate-terminated prepolymer obtained by reaction of a polyol with 3,3?-dimethylbiphenyl-4,4?-diisocyanate, with a foaming agent comprising a mixture of water, a low-molecular weight glycol having a molecular weight of 48-200, and a high-molecular weight glycol having a number average molecular weight Mn of 1000-3000 under stirring to conduct foaming reaction. The polyurethane elastomer foams so produced can have a high durability, particularly under a high load, even though a low-cost, easy-to-handle diisocyanate compound is used.

Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip is corrected and the board is connected, the bumps are compressed, and the insulating resin is hardened.

Abstract: Polyurethane elastomer foams can be prepared by mixing an isocyanate-terminated prepolymer obtained by reaction of a polyol with 3,3?-dimethylbiphenyl-4,4?-diisocyanate, with a foaming agent comprising a mixture of water, a low-molecular weight glycol having a molecular weight of 48-200, and a high-molecular weight glycol having a number average molecular weight Mn of 1000-3000 under stirring to conduct foaming reaction. The polyurethane elastomer foams so produced can have a high durability, particularly under a high load, even though a low-cost, easy-to-handle diisocyanate compound is used.

Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.

Abstract: A storage device which limits the partition of the logical memory devices for computers in accordance with properties such as reliability. An access control approves an access only to the logical memory device which was partitioned referring to an access control table. An access control setting control renews the access control table so as to partition the assigned logical memory devices to the assigned computer when the assigned logical memory devices can be partitioned.

Abstract: An electronic component and a circuit formation article are bonded together with a bonding material containing resin interposed therebetween. In a state that bumps of an electronic-component bonding region and electrodes of the circuit formation article are in mutual electrical contact, the electronic component and the circuit formation article are thermocompression-bonded to each other upon curing of the bonding material. A bonding-material flow regulating member of the electronic-component bonding region regulates flow of the bonding material toward a peripheral portion of the electronic-component bonding region during bonding of the circuit formation article to the electronic component.

Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.

Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.

Abstract: A semiconductor element mounting method is provided with high productivity. The method includes forming bumps on electrodes of a wafer in which a plurality of semiconductor elements have been formed, temporarily compression-bonding the wafer and an interposer via an insulative resin, curing the resin by performing heating and pressurization so that the wafer and the interposer are finally compression-bonded, wherein the electrodes of the wafer and electrodes of the interposer are bonded to each other, respectively, and wherein insulative resin overflowing from between the wafer and the interposer flows into grooves disposed so as to be coincident with dicing lines of the wafer, thus providing a uniform flow of the insulative resin, and thereafter, cutting and separating this bonded unit into individual semiconductor elements.

Abstract: A storage device which limits the partition of the logical memory devices for computers in accordance with the condition of partition which was defined to the properties such as reliability and the storage device so that the logical memory devices are unable to be utilized for uses other than objectives, a control method for partitioning the logical memory devices of the storage device and a control program product for partitioning the logical memory devices of the storage device. An access control means approves an access only to the logical memory device which was partitioned referring to an access control table. An access control setting means renews the access control table so as to partition the assigned logical memory devices to the assigned computer when the assigned logical memory devices can be partitioned.

Abstract: A multilayered circuit board and a method of forming the multilayered circuit board are provided. In a first circuit forming process, a first circuit is formed on an insulating board with a conductor; in a circuit embedding process, the first circuit is embedded in the insulating board so as to have a predetermined surface flatness and a predetermined parallelism; in a masking process, a pilot hole for a via hole is masked at a part of a surface of the circuit; in an insulating layer forming process P5p, an insulating material is applied as a layer to the surface except that portion thereof covered by the mask; in an insulating material layer flattening process, the surface of the insulating material layer is flattened so as to have the predetermined surface flatness and the predetermined parallelism; and in a pilot hole forming process, the mask is removed.

Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.

Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is corrected, the bumps are compressed, and the insulating resin is hardened.

Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.

Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.

Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.

Abstract: An integral type electronic device is formed from a first board and a second board by storing and holding electronic components in component storage parts of the first board, and then electrically connecting the second board to the electronic components. An arrangement accuracy of the electronic components is determined on a basis of an arrangement accuracy of the component storage parts, and the electronic components stored and held in the component storage parts are limited in motion.

Abstract: An integral type electronic component is formed of a first board and a second board by storing and holding electronic components to component storage parts of the first board and electrically connecting the second board to the electronic components. An arrangement accuracy of the electronic components is determined on the basis of an arrangement accuracy of the component storage parts, and the electronic components stored in the component storage parts are limited in motion. The electronic components can be arranged highly accurately and simply at low costs in a short time in comparison with the conventional art by being simply inserted to the component storage parts.

Abstract: A strengthening land is formed on a semiconductor chip-mounting board corresponding to a non-operating electrode on a semiconductor chip. The strengthening land and the non-operating electrode are bonded with each other, thereby improving a bonding strength between the semiconductor chip and the semiconductor chip-mounting board.

Abstract: A multilayered circuit board and a method of forming the multilayer circuit board are provided. In a first circuit forming process P1p, a first circuit 12a is formed on an insulating board 11a with a conductor 12a; in a circuit embedding process P2p, the first circuit 12a is embedded in the insulating board 11a so as to have a predetermined surface flatness S and a predetermined parallelism P; in a masking process P4p, a pilot hole 15, 20 for a via hole 4, 4a is masked at a part of the surface of the circuit 12a; in an insulating layer forming process P5p, an insulating material 11b is applied as a layer to the surface except the mask 14; in an insulating material layer flattening process, the surface of the insulating material layer 11b is flattened so as to have the predetermined surface flatness S and the predetermined parallelism P; and in a pilot hole forming process, the mask 14 is removed.