Abstract: Strap lines are provided in a layer above word lines so that the word lines and the strap lines are connected to each other in strapping regions separately provided at the ends of memory cell array portions in a conventional semiconductor memory device having a problem wherein the area of the memory cell array portions is increased. Each memory cell is formed of a MOS transistor and a MOS capacitor in a layout of a memory cell array portion according to a standard CMOS process. Memory cells of this structure have a sufficiently large pitch between bit lines and, therefore, contacts for connecting word lines to strap lines in an upper layer are provided between the bit lines, as low resistance metal wires, in the same layer as the bit lines.

Abstract: A semiconductor memory device includes memory array, first and second rows of sense amplifiers and selector. The memory array has first and second ports. The first and second rows of sense amplifiers are associated with the first and second ports, respectively. Responsive to a port selection signal, the selector selects the first or second port, through which burst data should be transferred, and couples the first or second row of sense amplifiers, associated with the port selected, to a data input or output circuit. If the selector has selected the first port, the device performs a refresh operation on the array using the second row of sense amplifiers while transferring the burst data through the first port. If the selector has selected the second port, the device performs the refresh operation on the array using the first row of sense amplifiers while transferring the burst data through the second port.

Abstract: A semiconductor memory device includes memory array, first and second rows of sense amplifiers and selector. The memory array has first and second ports. The first and second rows of sense amplifiers are associated with the first and second ports, respectively. Responsive to a port selection signal, the selector selects the first or second port, through which burst data should be transferred, and couples the first or second row of sense amplifiers, associated with the port selected, to a data input or output circuit. If the selector has selected the first port, the device performs a refresh operation on the array using the second row of sense amplifiers while transferring the burst data through the first port. If the selector has selected the second port, the device performs the refresh operation on the array using the first row of sense amplifiers while transferring the burst data through the second port.