Patents by Inventor Hiroyuki Sanda
Hiroyuki Sanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11798633Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.Type: GrantFiled: May 21, 2021Date of Patent: October 24, 2023Assignee: Micron Technology, Inc.Inventors: Randy J. Koval, Hiroyuki Sanda
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Publication number: 20210280255Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.Type: ApplicationFiled: May 21, 2021Publication date: September 9, 2021Inventors: Randy J. Koval, Hiroyuki Sanda
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Patent number: 11037633Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.Type: GrantFiled: April 29, 2019Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Randy J. Koval, Hiroyuki Sanda
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Patent number: 10622450Abstract: A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.Type: GrantFiled: June 28, 2018Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Randy Koval, Srikant Jayanti, Hiroyuki Sanda, Meng-Wei Kuo, Srivardhan Gowda, Krishna Parat
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Patent number: 10453535Abstract: Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.Type: GrantFiled: October 26, 2015Date of Patent: October 22, 2019Assignee: Intel CorporationInventors: Shantanu R. Rajwade, Akira Goda, Pranav Kalavade, Krishna K. Parat, Hiroyuki Sanda
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Publication number: 20190252026Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Randy J. Koval, Hiroyuki Sanda
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Patent number: 10297325Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.Type: GrantFiled: January 5, 2018Date of Patent: May 21, 2019Assignee: Micron Technology, Inc.Inventors: Randy J. Koval, Hiroyuki Sanda
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Publication number: 20190043960Abstract: A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 28, 2018Publication date: February 7, 2019Inventors: Randy Koval, Srikant Jayanti, Hiroyuki Sanda, Meng-Wei Kuo, Srivardhan Gowda, Krishna Parat
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Patent number: 10128262Abstract: An apparatus is described having a memory. The memory includes a vertical stack of storage cells, where, a first storage node at a lower layer of the vertical stack has a different structural design than a second storage node at a higher layer of the vertical stack.Type: GrantFiled: December 26, 2015Date of Patent: November 13, 2018Assignee: Intel CorporationInventors: Randy J. Koval, Hiroyuki Sanda
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Publication number: 20180130536Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.Type: ApplicationFiled: January 5, 2018Publication date: May 10, 2018Inventors: Randy J. Koval, Hiroyuki Sanda
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Patent number: 9875801Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.Type: GrantFiled: February 3, 2014Date of Patent: January 23, 2018Assignee: Micron Technology, Inc.Inventors: Randy J. Koval, Hiroyuki Sanda
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Publication number: 20170186765Abstract: An apparatus is described having a memory. The memory includes a vertical stack of storage cells, where, a first storage node at a lower layer of the vertical stack has a different structural design than a second storage node at a higher layer of the vertical stack.Type: ApplicationFiled: December 26, 2015Publication date: June 29, 2017Inventors: Randy J. Koval, Hiroyuki Sanda
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Publication number: 20170117049Abstract: Systems, apparatuses and methods may provide for identifying a target sub-block of NAND strings to be partially or wholly erased in memory and triggering a leakage current condition in one or more target select gate drain-side (SGD) devices associated with the target sub-block. Additionally, the leakage current condition may be inhibited in one or more remaining SGD devices associated with remaining sub-blocks of NAND strings in the memory. In one example, triggering the leakage current condition in the one or more target SGD devices includes setting a gate voltage of the one or more target SGD devices to a value that generates a reverse voltage that exceeds a threshold corresponding to the leakage current condition.Type: ApplicationFiled: October 26, 2015Publication date: April 27, 2017Applicant: INTEL CORPORATIONInventors: Shantanu R. Rajwade, Akira Goda, Pranav Kalavade, Krishna K. Parat, Hiroyuki Sanda
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Patent number: 9543024Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before erasure. In one instance, the method includes receiving a request to erase information in a portion of the nonvolatile memory device, in which the portion includes a plurality of storage units, determining whether one or more storage units of the plurality of storage units included in the portion of the non-volatile memory device are programmed, pre-programming the portion of the non-volatile memory device if the one or more storage units are determined to be programmed, and erasing the pre-programmed portion of the non-volatile memory device. A number of determined programmed storage units may not exceed a predetermined value. Other embodiments may be described and/or claimed.Type: GrantFiled: March 29, 2012Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Hiroyuki Sanda, Kiran Pangal, Xin Guo, Kaoru Naganuma
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Patent number: 9424936Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for providing an apparatus comprising a memory array, to which bias voltage may be provided to reduce leakage current. In one embodiment, the apparatus may comprise a three-dimensional (3D) memory array having at least first and second blocks; and circuitry coupled with the 3D memory array to access the 3D memory array. The circuitry may include circuit to deselect the first block and select the second block, and supply a first bias voltage to the deselected first block and a second bias voltage to the selected second block, to reduce leakage current in the 3D memory array. The first bias voltage may be different than the second bias voltage. Other embodiments may be described and/or claimed.Type: GrantFiled: March 23, 2015Date of Patent: August 23, 2016Assignee: Intel CorporationInventors: Toru Tanzawa, Akira Goda, Shigekazu Yamada, Hiroyuki Sanda
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Publication number: 20150221347Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.Type: ApplicationFiled: February 3, 2014Publication date: August 6, 2015Applicant: Micron Technology, Inc.Inventors: Randy J. Koval, Hiroyuki Sanda
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Patent number: 9047187Abstract: Defect management logic extends a useful life of a memory system. For example, as discussed herein, failure detection logic detects occurrence of a failure in a memory system. Defect management logic determines a type of the failure such as whether the failure is an infant mortality type failure or a late-life type of failure. Depending on the type of failure, the defect management logic performs different operations to extend the useful life of the memory system. For example, for early life failures, the defect management logic can retire a portion of the block including the failure. For late life failures, due to excessive reads/writes, the defect management logic can convert the failing block from operating in a first bit-per-cell storage density mode to operating in a second bit-per-cell storage density mode.Type: GrantFiled: June 28, 2012Date of Patent: June 2, 2015Assignee: Intel CorporationInventors: Xin Guo, Yogesh B. Wakchaure, Kiran Pangal, Hiroyuki Sanda
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Publication number: 20140297924Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before erasure. In one instance, the method includes receiving a request to erase information in a portion of the nonvolatile memory device, in which the portion includes a plurality of storage units, determining whether one or more storage units of the plurality of storage units included in the portion of the non-volatile memory device are programmed, pre-programming the portion of the non-volatile memory device if the one or more storage units are determined to be programmed, and erasing the pre-programmed portion of the non-volatile memory device. A number of determined programmed storage units may not exceed a predetermined value. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 29, 2012Publication date: October 2, 2014Inventors: Hiroyuki Sanda, Kiran Pangal, Xin Guo, Kaoru Naganuma
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Publication number: 20140006847Abstract: Defect management logic extends a useful life of a memory system. For example, as discussed herein, failure detection logic detects occurrence of a failure in a memory system. Defect management logic determines a type of the failure such as whether the failure is an infant mortality type failure or a late-life type of failure. Depending on the type of failure, the defect management logic performs different operations to extend the useful life of the memory system. For example, for early life failures, the defect management logic can retire a portion of the block including the failure. For late life failures, due to excessive reads/writes, the defect management logic can convert the failing block from operating in a first bit-per-cell storage density mode to operating in a second bit-per-cell storage density mode.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Inventors: Xin Guo, Yogesh B. Wakchaure, Kiran Pangal, Hiroyuki Sanda