Abstract: By mounting, on a semiconductor integrated circuit, a clock stability waiting circuit 4 for deciding whether a clock signal generated by a high speed clock generating circuit 2 is stable or not, a scan pass control circuit 7 capable of switching a scan pass structure based on a signal output from the clock stability waiting circuit 4 and an activation control circuit 6 capable of switching an order circuit to be activated based on the signal output from the clock stability waiting circuit 4, it is possible to carry out a parallel test in a stability waiting time having a high speed clock. Moreover, it is possible to externally monitor a signal capable of deciding a stability of a high speed clock. Therefore, it is easy to decide whether a failure is caused by a high speed clock generating portion or an internal circuit.