Patents by Inventor Hiroyuki Shinogi

Hiroyuki Shinogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9034729
    Abstract: An object of the invention is to provide a smaller semiconductor device of which the manufacturing process is simplified and the manufacturing cost is reduced and a method of manufacturing the same. Furthermore, an object of the invention is to provide a semiconductor device having a cavity. A first supporting body 5 having a penetration hole 6 penetrating it from the front surface to the back surface is attached to a front surface of a semiconductor substrate 2 with an adhesive layer 4 being interposed therebetween. A device element 1 and wiring layers 3 are formed on the front surface of the semiconductor substrate 2. A second supporting body 7 is attached to the first supporting body 5 with an adhesive layer 8 being interposed therebetween so as to cover the penetration hole 6. The device element 1 is sealed in a cavity 9 surrounded by the semiconductor substrate 2, the first supporting body 5 and the second supporting body 7.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Hiroshi Yamada, Katsuhiko Kitagawa, Kazuo Okada, Yuichi Morita, Hiroyuki Shinogi, Shinzo Ishibe, Yoshinori Seki, Takashi Noma
  • Patent number: 8766408
    Abstract: A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor substrate through an adhesive layer. Then, there is formed a protection layer that has an opening at a location corresponding to the pad electrode and covers a side surface and a back surface of the semiconductor substrate. A conductive terminal is formed on the pad electrode at the location corresponding to the opening formed in the protection layer. No wiring layer or conductive terminal is formed on the back surface of the semiconductor substrate. A conductive terminal is formed on a periphery of the supporter outside of and next to the side surface of the semiconductor substrate.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: July 1, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Takashi Noma, Shigeki Otsuka, Yuichi Morita, Kazuo Okada, Hiroshi Yamada, Katsuhiko Kitagawa, Noboru Okubo, Shinzo Ishibe, Hiroyuki Shinogi
  • Patent number: 8686526
    Abstract: The invention is directed to providing a semiconductor device receiving a blue-violet laser, of which the reliability and yield are enhanced. A device element converting a blue-violet laser into an electric signal is formed on a front surface of a semiconductor substrate. An optically transparent substrate is attached to the front surface of the semiconductor substrate with an adhesive layer being interposed therebetween. The adhesive layer contains transparent silicone. Since the front surface of the device element is covered by the optically transparent substrate, foreign substances are prevented from adhering to the front surface of the device element. Furthermore, the adhesive layer is covered by the optically transparent substrate. This prevents the adhesive layer from being exposed to outside air, thereby preventing the degradation of the adhesive layer 6 due to a blue-violet laser.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Katsuhiko Kitagawa, Hiroyuki Shinogi, Shinzo Ishibe, Hiroshi Yamada
  • Patent number: 8410577
    Abstract: The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed on the side and back surfaces of the semiconductor substrate, and a capacitor electrode is formed between the back surface of the semiconductor substrate and the second insulation film, contacting the back surface of the semiconductor substrate. The second insulation film is covered by wiring layers electrically connected to the pad electrodes, and the wiring layers and the capacitor electrode overlap with the second insulation film being interposed therebetween. Thus, the capacitor electrode, the second insulation film and the wiring layers form capacitors.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: April 2, 2013
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Katsu Horikoshi, Hisayoshi Uchiyama, Takashi Noma, Yoshinori Seki, Hiroshi Yamada, Shinzo Ishibe, Hiroyuki Shinogi
  • Patent number: 8373278
    Abstract: Semiconductor dice judged as good dice are stacked on a base substrate in which through holes and through hole electrodes are formed. Next, a protection layer to cover the semiconductor dice is formed. It is preferable that the protection layer is composed of a plurality of resin layers (a first resin layer and a second resin layer) that are different, in hardness from each other. Then, a conductive terminal that is connected with the through hole electrode is formed on a back surface of the base substrate. Next, the second resin layer and the base substrate are cut along predetermined dicing lines and separated into individual semiconductor devices in chip form. A process step of separation into the semiconductor devices is performed while each of the semiconductor dice is mounted on the base substrate in wafer form.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: February 12, 2013
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Hiroyuki Shinogi
  • Patent number: 8148811
    Abstract: This invention is directed to offer a semiconductor device in which a cavity space is easily provided in a specific region when a supporting member is bonded to a semiconductor substrate through an adhesive layer, and its manufacturing method. A resist layer is applied to an entire top surface of the semiconductor substrate 2, and exposure to transfer a pattern is performed. By subsequent development and selective removal of the resist layer, the resist layer is formed into a shape of a plurality of columnar structures 4. Then, an adhesive material made of an epoxy resin or the like is applied to the entire top surface of the semiconductor substrate 2. The adhesive material is gathered around the columnar structures 4 by itself to form an adhesive layer 5. Therefore, in contrast, the adhesive layer 5 does not deposit in a region where the cavity is to be formed. Then, the supporting member 6 is bonded through the columnar structures 4 and the adhesive layer 5.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: April 3, 2012
    Assignees: Semiconductor Components Industries, LLC, SANYO Semiconductor Co., Ltd.
    Inventors: Hiroyuki Shinogi, Katsuhiko Kitagawa, Kazuo Okada, Hiroshi Yamada
  • Patent number: 8105856
    Abstract: Cost is reduced and reliability is improved with a BGA (Ball Grid Array) type semiconductor device which has ball-shaped conductive terminals. A first wiring is formed on an insulation film which is formed on a surface of a semiconductor die. A glass substrate is bonded over the surface of the semiconductor die, and a side surface and a back surface of the semiconductor die are covered with an insulation film. A second wiring is connected to a side surface or a back surface of the first wiring and extending over the back surface of the semiconductor die. A conductive terminal such as a bump is formed on the second wiring.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: January 31, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Takashi Noma, Hiroyuki Shinogi, Nobuyuki Takai, Katsuhiko Kitagawa, Ryoji Tokushige, Takayasu Otagaki, Tatsuya Ando, Mitsuru Okigawa
  • Patent number: 8102039
    Abstract: This invention is directed to offer a package type semiconductor device that can realize a smaller size device and its manufacturing method as well as a small stacked layer type semiconductor device and its manufacturing method. A device component 1 and a pad electrode 4 electrically connected with the device component 1 are formed on a semiconductor substrate 2. A supporting member 7 is bonded to a surface of the semiconductor substrate 2 through an adhesive layer 6. There is formed a through-hole 15 in the supporting member 7 penetrating from its top surface to a back surface. Electrical connection with another device is made possible through the through-hole 15. A depressed portion 12 is formed in a partial region of the top surface of the supporting member 7. Therefore, all or a portion of another device or a component can be disposed utilizing a space in the depressed portion 12.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: January 24, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Takashi Noma, Yuichi Morita, Hiroshi Yamada, Kazuo Okada, Katsuhiko Kitagawa, Noboru Okubo, Shinzo Ishibe, Hiroyuki Shinogi
  • Patent number: 8044440
    Abstract: The invention is directed to providing a smaller semiconductor device formed as an optical sensor including a light receiving portion and a light emitting portion. A light receiving portion and a light emitting portion are disposed on a front surface of a semiconductor substrate for forming a semiconductor die, and a supporting body is attached to these so as to face these with an adhesive being interposed therebetween. A first opening exposing the light receiving portion from the front side of the supporting body is provided, and in a separated position therefrom, a second opening exposing the light emitting portion from the front side of the supporting body is provided. A first electrode and a second electrode are further disposed on the front surface of the semiconductor substrate, and bump electrodes electrically connected to these are disposed on the back surface of the semiconductor substrate.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: October 25, 2011
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Takashi Noma, Hiroyuki Shinogi
  • Patent number: 7986021
    Abstract: The invention provides a semiconductor device that solves a problem of reflection of a pattern of a wiring formed on a back surface of a semiconductor substrate on an output image. A reflection layer is formed between a light receiving element and a wiring layer, that reflects an infrared ray toward a light receiving element the without transmitting it to the wiring layer, the infrared ray entering from a light transparent substrate toward the wiring layer through a semiconductor substrate. The reflection layer is formed at least in a region under the light receiving element uniformly or only under the light receiving element. Alternatively, an anti-reflection layer having a function of absorbing the entering infrared ray to prevent transmission thereof may be formed instead of the reflection layer.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: July 26, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Kazuo Okada, Katsuhiko Kitagawa, Takashi Noma, Shigeki Otsuka, Hiroshi Yamada, Shinzo Ishibe, Yuichi Morita, Noboru Okubo, Hiroyuki Shinogi, Mitsuru Okigawa
  • Patent number: 7981807
    Abstract: Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: July 19, 2011
    Assignee: SANYO Electric Co., Ltd.
    Inventors: Akira Suzuki, Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao, Shinzo Ishibe, Shigeki Otsuka, Keiichi Yamaguchi
  • Patent number: 7969007
    Abstract: A semiconductor device with improved moisture resistance and its manufacturing method as well as a manufacturing method of a semiconductor device which simplifies a manufacturing process and improves productivity are offered. This invention offers a CSP type semiconductor device and its manufacturing method that can prevent moisture and the like from infiltrating into it to attain high reliability by covering a side surface of a semiconductor chip with a thick protection layer. This invention also offers a highly productive manufacturing method of semiconductor devices by which a supporter bonded to semiconductor dice is etched from a back surface-side of the supporter so that the semiconductor devices can be separated without dicing.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: June 28, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Takashi Noma, Hiroyuki Shinogi, Noboru Okubo
  • Patent number: 7944015
    Abstract: The invention provides a semiconductor device having high reliability and a method of manufacturing the same. The semiconductor device of the invention has pad electrodes formed on a semiconductor die near the side surface portion thereof and connected to a semiconductor integrated circuit or the like in the semiconductor die, a supporting body formed on the pad electrodes, an insulation film formed on the side and back surface portions of the semiconductor die, wiring layers connected to the back surfaces of the pad electrodes and extending from the side surface portion onto the back surface portion of the semiconductor die so as to contact the insulation film, and a second protection film formed on the side surface portion of the supporting body.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: May 17, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Katsuhiko Kitagawa, Hiroyuki Shinogi
  • Patent number: 7759779
    Abstract: The invention enhances moisture resistance between a supporting body and an adhesive layer to enhance the reliability of a semiconductor device. A semiconductor device of the invention has a first insulation film formed on a semiconductor element, a first wiring formed on the first insulation film, a supporting body formed on the semiconductor element with an adhesive layer being interposed therebetween, a third insulation film covering the back surface of the semiconductor element onto the side surface thereof and the side surface of the adhesive layer, a second wiring connected to the first wiring and extending onto the back surface of the semiconductor element with the third insulation film being interposed therebetween, and a protection film formed on the second wiring.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: July 20, 2010
    Assignees: Sanyo Semiconductor Co., Ltd., Sanyo Electric Co., Ltd.
    Inventors: Kazuo Okada, Hiroyuki Shinogi, Yoshinori Seki, Hiroshi Yamada
  • Publication number: 20100164086
    Abstract: This invention is directed to offer a package type semiconductor device that can realize a smaller size device and its manufacturing method as well as a small stacked layer type semiconductor device and its manufacturing method. A device component 1 and a pad electrode 4 electrically connected with the device component 1 are formed on a semiconductor substrate 2. A supporting member 7 is bonded to a surface of the semiconductor substrate 2 through an adhesive layer 6. There is formed a through-hole 15 in the supporting member 7 penetrating from its top surface to a back surface. Electrical connection with another device is made possible through the through-hole 15. A depressed portion 12 is formed in a partial region of the top surface of the supporting member 7. Therefore, all or a portion of another device or a component can be disposed utilizing a space in the depressed portion 12.
    Type: Application
    Filed: August 2, 2007
    Publication date: July 1, 2010
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Takashi Noma, Yuichi Morita, Hiroshi Yamada, Kazuo Okada, Katsuhiko Kitagawa, Noboru Okubo, Shinzo Ishibe, Hiroyuki Shinogi
  • Patent number: 7719102
    Abstract: A manufacturing method of a semiconductor device of this invention includes forming metal pads on a Si substrate through a first oxide film, bonding the Si substrate and a holding substrate which bolsters the Si substrate through a bonding film, forming an opening by etching the Si substrate followed by forming a second oxide film on a back surface of the Si substrate and in the opening, forming a wiring connected to the metal pads after etching the second oxide film, forming a conductive terminal on the wiring, dicing from the back surface of the Si substrate to the bonding film and separating the Si substrate and the holding substrate.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: May 18, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Noma, Hiroyuki Shinogi, Yukihiro Takao
  • Publication number: 20100044821
    Abstract: This invention offers a semiconductor device to measure a luminance for the visible wavelength range of light components and its manufacturing method which reduce its manufacturing cost. A first light-receiving element and a second light-receiving element are formed in a semiconductor substrate. Then, there is formed an arithmetic circuit that calculates a difference between a value of an electric current corresponding to an amount of light detected by the first light-receiving element (that is, a value of an electric current representing a relative sensitivity against the light) and a value of an electric current corresponding to an amount of light detected by the second light-receiving element (that is, a value of an electric current representing a relative sensitivity against the light).
    Type: Application
    Filed: August 10, 2009
    Publication date: February 25, 2010
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventors: Takashi Noma, Yoshimasa Amatatsu, Yoshinori Seki, Hiroyuki Shinogi
  • Patent number: 7662670
    Abstract: A glass substrate is bonded through a resin to the top surface of a semiconductor wafer on which a first wiring is formed. A V-shaped groove is formed by notching from the back surface of the wafer. A second wiring connected with the first wiring and extending over the back surface of the wafer is formed. A protection film composed of an organic resin or a photoresist layer to provide protection with an opening is formed on the second wiring by spray coating. A conductive terminal is formed by screen printing using the protection film as a solder mask. A cushioning material may be formed on the back surface of the wafer by spray coating.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: February 16, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Noma, Hiroyuki Shinogi, Akira Suzuki, Yoshinori Seki, Koichi Kuhara, Yukihiro Takao, Hiroshi Yamada
  • Publication number: 20090321903
    Abstract: This invention is directed to offer a semiconductor device in which a cavity space is easily provided in a specific region when a supporting member is bonded to a semiconductor substrate through an adhesive layer, and its manufacturing method. A resist layer is applied to an entire top surface of the semiconductor substrate 2, and exposure to transfer a pattern is performed. By subsequent development and selective removal of the resist layer, the resist layer is formed into a shape of a plurality of columnar structures 4. Then, an adhesive material made of an epoxy resin or the like is applied to the entire top surface of the semiconductor substrate 2. The adhesive material is gathered around the columnar structures 4 by itself to form an adhesive layer 5. Therefore, in contrast, the adhesive layer 5 does not deposit in a region where the cavity is to be formed. Then, the supporting member 6 is bonded through the columnar structures 4 and the adhesive layer 5.
    Type: Application
    Filed: August 22, 2007
    Publication date: December 31, 2009
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.
    Inventors: Hiroyuki Shinogi, Katsuhiko Kitagawa, Kazuo Okada, Hiroshi Yamada
  • Patent number: 7633133
    Abstract: This invention provides a semiconductor device that solves a problem that a pattern of a wiring formed on a back surface of a semiconductor substrate is reflected on an output image. A light receiving element (e.g. a CCD, an infrared ray sensor, a CMOS sensor, or an illumination sensor) is formed on a front surface of a semiconductor substrate, and a plurality of ball-shaped conductive terminals is disposed on a back surface of the semiconductor substrate. Each of the conductive terminals is electrically connected to a pad electrode on the front surface of the semiconductor substrate through a wiring layer. The wiring layer and the conductive terminal are formed on the back surface of the semiconductor substrate except in a region overlapping the light receiving element in a vertical direction, and are not disposed in a region overlapping the light receiving element.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: December 15, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takashi Noma, Kazuo Okada, Shinzo Ishibe, Katsuhiko Kitagawa, Yuichi Morita, Shigeki Otsuka, Hiroshi Yamada, Noboru Okubo, Hiroyuki Shinogi, Mitsuru Okigawa