Patents by Inventor Hiroyuki Takamiya
Hiroyuki Takamiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9151875Abstract: A touch panel which prevents Newton ring formation and glare, shows high transmission image clarity, prevents haze and has high visibility, and an optical film which is applicable to such a touch panel. An optical film comprising an optically-transparent substrate and at least one hard coat layer (A) disposed on a surface of the optically-transparent substrate, wherein a surface of the hard coat layer (A), which is opposite to a surface where the optically-transparent substrate is present, has an arithmetic mean roughness (Ra) defined in JIS B0601 (1994) of 0.025 to 0.05 ?m, and has 10 to 250 convex portions each having a height of 0.3 to 3 ?m in a 1.08 mm square area.Type: GrantFiled: November 29, 2010Date of Patent: October 6, 2015Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Hiroyuki Takamiya, Kenji Ueno, Seika Minakoshi
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Patent number: 8338890Abstract: A semiconductor device includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one of the semiconductor substrates. In the device, the through electrode is electrically connected with the plurality of electrostatic discharge protection circuits.Type: GrantFiled: November 30, 2009Date of Patent: December 25, 2012Assignee: Seiko Epson CorporationInventors: Takayuki Saiki, Shinya Sato, Hiroyuki Takamiya
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Patent number: 8310478Abstract: An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.Type: GrantFiled: June 30, 2006Date of Patent: November 13, 2012Assignee: Seiko Epson CorporationInventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Takayuki Saiki, Hiroyuki Takamiya
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Publication number: 20120243115Abstract: The present invention provides an optical layered body which prevents the occurrence of curling (warpage), has excellent durability while maintaining pencil hardness, and can prevent the degradation of durability of an image display screen by external light by using the optical layered body as a protective film of the image display screen.Type: ApplicationFiled: September 30, 2010Publication date: September 27, 2012Applicant: Dai Nippon Printing Co., Ltd.Inventors: Hiroyuki Takamiya, Kenji Ueno, Masataka Ino, Kenta Sato
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Publication number: 20120229423Abstract: A touch panel which prevents Newton ring formation and glare, shows high transmission image clarity, prevents haze and has high visibility, and an optical film which is applicable to such a touch panel. An optical film comprising an optically-transparent substrate and at least one hard coat layer (A) disposed on a surface of the optically-transparent substrate, wherein a surface of the hard coat layer (A), which is opposite to a surface where the optically-transparent substrate is present, has an arithmetic mean roughness (Ra) defined in JIS B0601 (1994) of 0.025 to 0.05 ?m, and has 10 to 250 convex portions each having a height of 0.3 to 3 ?m in a 1.08 mm square area.Type: ApplicationFiled: November 29, 2010Publication date: September 13, 2012Applicant: DAI NIPPON PRINTING CO., LTD.Inventors: Hiroyuki Takamiya, Kenji Ueno, Seika Minakoshi
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Patent number: 8247841Abstract: A semiconductor device includes: a plurality of semiconductor substrates that are layered; a through electrode penetrating through a predetermined semiconductor substrate of the semiconductor substrates and electrically connected with an external terminal of the semiconductor device; a circuit element provided on the predetermined semiconductor substrate; and an electrostatic discharge protection circuit also provided on the predetermined semiconductor substrate. In the device, wiring resistance between the electrostatic discharge protection circuit and the through electrode is smaller than wiring resistance between the circuit element and the through electrode.Type: GrantFiled: November 30, 2009Date of Patent: August 21, 2012Assignee: Seiko Epson CorporationInventors: Takayuki Saiki, Shinya Sato, Hiroyuki Takamiya
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Patent number: 8188544Abstract: An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.Type: GrantFiled: June 30, 2006Date of Patent: May 29, 2012Assignee: Seiko Epson CorporationInventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Takayuki Saiki, Hiroyuki Takamiya
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Patent number: 7974051Abstract: An interface circuit is provided between a first circuit block and a second circuit block that operates using a power supply system differing from that of the first circuit block. An electrostatic discharge protection circuit that include a PN diode and a diffused resistor is formed in order to prevent electrostatic discharge destruction of a gate insulating film of a transistor that forms the interface circuit. The electrostatic discharge protection circuit may be formed using the remaining basic cells of a gate array that forms the second circuit block. An electrostatic discharge protection circuit formed of a bidirectional diode may be connected between a first low-potential power supply and a second low-potential power supply.Type: GrantFiled: April 9, 2008Date of Patent: July 5, 2011Assignee: Seiko Epson CorporationInventors: Shinya Sato, Takayuki Saiki, Hiroyuki Takamiya
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Publication number: 20110128274Abstract: An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.Type: ApplicationFiled: February 8, 2011Publication date: June 2, 2011Applicant: SEIKO EPSON CORPORATIONInventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru ITO, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Takayuki Saiki, Hiroyuki Takamiya
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Publication number: 20100133678Abstract: A semiconductor device includes: a plurality of semiconductor substrates that are layered; a through electrode penetrating through a predetermined semiconductor substrate of the semiconductor substrates and electrically connected with an external terminal of the semiconductor device; a circuit element provided on the predetermined semiconductor substrate; and an electrostatic discharge protection circuit also provided on the predetermined semiconductor substrate. In the device, wiring resistance between the electrostatic discharge protection circuit and the through electrode is smaller than wiring resistance between the circuit element and the through electrode.Type: ApplicationFiled: November 30, 2009Publication date: June 3, 2010Applicant: SEIKO EPSON CORPORATIONInventors: Takayuki SAIKI, Shinya SATO, Hiroyuki TAKAMIYA
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Publication number: 20100133701Abstract: A semiconductor device includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one of the semiconductor substrates. In the device, the through electrode is electrically connected with the plurality of electrostatic discharge protection circuits.Type: ApplicationFiled: November 30, 2009Publication date: June 3, 2010Applicant: SEIKO EPSON CORPORATIONInventors: Takayuki SAIKI, Shinya SATO, Hiroyuki TAKAMIYA
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Publication number: 20080253045Abstract: An interface circuit is provided between a first circuit block and a second circuit block that operates using a power supply system differing from that of the first circuit block. An electrostatic discharge protection circuit that include a PN diode and a diffused resistor is formed in order to prevent electrostatic discharge destruction of a gate insulating film of a transistor that forms the interface circuit. The electrostatic discharge protection circuit may be formed using the remaining basic cells of a gate array that forms the second circuit block. An electrostatic discharge protection circuit formed of a bidirectional diode may be connected between a first low-potential power supply and a second low-potential power supply.Type: ApplicationFiled: April 9, 2008Publication date: October 16, 2008Applicant: SEIKO EPSON CORPORATIONInventors: Shinya SATO, Takayuki SAIKI, Hiroyuki TAKAMIYA
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Publication number: 20080252634Abstract: An integrated circuit device includes a first circuit block that includes low-voltage transistors (LVTr) and operates using a first high-potential power supply voltage and a first low-potential power supply voltage, a second circuit block that includes low-voltage transistors (LVTr) and operates using a second high-potential power supply voltage and a second low-potential power supply voltage that differ in power supply system from the first circuit block, and an interface circuit (I/O buffer) provided between the first circuit block and the second circuit block. The interface circuit (I/O buffer) includes medium-voltage transistors (MVTr: transistors of which the thickness of the gate insulating film is larger than that of the low-voltage transistors (LVTr)). An electrostatic discharge protection circuit formed of bidirectional diodes is provided between a first and second low-potential power supply nodes.Type: ApplicationFiled: April 9, 2008Publication date: October 16, 2008Applicant: SEIKO EPSON CORPORATIONInventors: Shinya Sato, Takayuki Saiki, Hiroyuki Takamiya, Masaaki Abe
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Publication number: 20070000971Abstract: An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.Type: ApplicationFiled: June 30, 2006Publication date: January 4, 2007Applicant: SEIKO EPSON CORPORATIONInventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Takayuki Saiki, Hiroyuki Takamiya
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Publication number: 20070002509Abstract: An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.Type: ApplicationFiled: June 30, 2006Publication date: January 4, 2007Applicant: Seiko Epson CorporationInventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Takayuki Saiki, Hiroyuki Takamiya
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Publication number: 20040013558Abstract: A process for compacting a green compact includes the steps of applying a higher fatty acid-based lubricant to an inner surface of a die, filling a raw material powder whose major component is an active metallic element into the die, compacting the raw material powder by warm pressurizing to make a green compact, and ejecting the green compact from the die, whereby the resulting green compact has a high density. It is possible to form active metallic powders including an active metallic element such as Ti and Al by pressurizing by high pressures, and to produce high-density green compacts which have not been available conventionally.Type: ApplicationFiled: July 10, 2003Publication date: January 22, 2004Applicant: Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Mikio Kondoh, Takashi Saito, Hiroyuki Takamiya
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Patent number: 6607693Abstract: A titanium alloy according to the present invention is characterized in that it comprises an element of Va group (the vanadium group) in an amount of 30-60% by weight and the balance of titanium substantially, exhibits an average Young's modulus of 75 GPa or less, and exhibits a tensile elastic limit strength of 700 MPa or more. This titanium alloy can be used in a variety of products, which are required to exhibit a low Young's modulus, a high elastic deformability and a high strength, in a variety of fields.Type: GrantFiled: February 12, 2001Date of Patent: August 19, 2003Assignee: Kabushiki Kaisha Toyota Chuo KenkyushoInventors: Takashi Saito, Tadahiko Furuta, Kazuaki Nishino, Hiroyuki Takamiya
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Patent number: 6551371Abstract: A titanium-based composite material according to the present invention is characterized in that it comprises: a matrix containing a titanium (Ti) alloy as a major component, and titanium compound particles and/or rare-earth element compound particles dispersed in the matrix, wherein the matrix contains 3.0-7.0% by weight of aluminum (Al), 2.0-6.0% by weight of tin (Sn), 2.0-6.0% by weight of zirconium (Zr), 0.1-0.4% by weight of silicon (Si) and 0.1-0.5% by weight of oxygen (O), the titanium compound particles occupy 1-10% by volume, and the rare-earth element compound particles occupy 3% by volume or less. With this arrangement, it is possible to obtain a titanium material, which is good in terms of the heat resistance, hot working property, specific strength, and so on.Type: GrantFiled: January 22, 2001Date of Patent: April 22, 2003Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyota Jidosha Kabushiki KaishaInventors: Tadahiko Furuta, Takashi Saito, Hiroyuki Takamiya, Toshiya Yamaguchi
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Patent number: 6150455Abstract: A thermostable polymer electrolyte gel containing an acrylonitrile polymer, an electrolyte and a solvent, the acrylonitrile polymer having an acrylonitrile content of from 89 wt % to 98 wt % and meeting the following relationship:1,040,000-(A.times.10,000).ltoreq.B.ltoreq.1,490,000-(A.times.10,000)where A is the acrylonitrile content in wt % and B is the weight average molecular weight of the acrylonitrile polymer, the polymer electrolyte gel having an ion conductivity of 10.sup.-3 S/cm or higher at 20.degree. C., exhibiting the "retention of shape" in a thermostability test, and containing the acrylonitrile polymer in a proportion of from 3 wt % to 9 wt %. The thermostable polymer electrolyte gel can be produced by dissolving an acrylonitrile polymer and an electrolyte in a solvent to prepare a solution of the polymer, and cooling the polymer solution to a temperature of 0.degree. C. or lower.Type: GrantFiled: November 4, 1997Date of Patent: November 21, 2000Assignees: Toyo Boseki Kabushiki Kaisha, Japan Exlan Company, Ltd.Inventors: Hiroyuki Takamiya, Ryosuke Nishida, Tatsuaki Sumitani
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Patent number: 6143390Abstract: A low-temperature regenerative type moisture absorbing element of fast moisture absorbing and releasing speed, capable of regenerating at 110.degree. C. or less and having a sufficiently high moisture absorbing and releasing performance in spite of small size is provided. A low-temperature regenerative type moisture absorbing element is mainly composed of high moisture absorbing and releasing polymeric compound with the content of salt type carboxyl group adjusted to a specific amount, and further comprises plural gas passages, of which regeneration temperature is 110.degree. C. or less. It is hence possible to provide a moisture absorbing element of small size, high efficiency, and energy-saving type, being excellent in moisture absorbing and releasing performance, and easily capable of removing absorbed moisture at low temperature which was impossible with the conventional moisture absorbing element.Type: GrantFiled: August 5, 1996Date of Patent: November 7, 2000Assignee: Toyo Boseki Kabushiki KaishaInventors: Hiroyuki Takamiya, Tatsuaki Sumitani, Masao Ieno