Abstract: An imaging device according to an embodiment of the present disclosure includes: a semiconductor substrate having a first surface and a second surface that are opposed to each other, and including a plurality of pixels and a plurality of photoelectric converters, the plurality of pixels disposed in a matrix, and the plurality of photoelectric converters that generates, through photoelectric conversion, an electric charge corresponding to an amount of received light for each of the pixels; a first isolation section that is provided between adjacent pixels of the pixels and electrically and optically isolates the adjacent pixels from each other, a second isolation section that is provided between adjacent photoelectric converters in the pixel of the photoelectric converters and electrically isolates the adjacent photoelectric converters from each other; and an electrode layer provided on side of the first surface of the semiconductor substrate to extend over adjacent photoelectric converters of the photoelectri

Abstract: A photodetector according to an embodiment of the present disclosure including a plurality of photoelectric conversion sections that is provided to a semiconductor substrate. The photoelectric conversion sections each include a first region of a first electrical conduction type that is provided on a first surface side of the semiconductor substrate, a second region of a second electrical conduction type that is provided on a second surface side of the semiconductor substrate opposite to the first surface, a third region of a third electrical conduction type that is provided in a region between the first region and the second region of the semiconductor substrate, a first electrode that extends from the second surface in a thickness direction of the semiconductor substrate, a pixel separation layer having an insulation property, and a second electrode that is electrically coupled to the second region from the second surface side. The third region absorbs incident light.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P?pocket regions 17 and N?pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P?pocket regions 17 and the N?pocket regions 27.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P? pocket regions 17 and N? pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P? pocket regions 17 and the N? pocket regions 27.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P? pocket regions 17 and N? pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P? pocket regions 17 and the N? pocket regions 27.

Abstract: A semiconductor device includes a semiconductor substrate, an insulated gate type transistor formed in the semiconductor substrate, and an insulated gate type capacitor formed in the semiconductor substrate. The insulated gate type transistor includes a gate insulating film of the transistor selectively formed on the semiconductor substrate, a gate electrode of the transistor formed on the gate insulating film of the transistor, and source-drain regions formed to interpose a body region of the transistor provided under the gate electrode of the transistor in a surface of the semiconductor substrate. The insulated gate type capacitor includes a gate insulating film of the capacitor selectively formed on the semiconductor substrate, a gate electrode of the capacitor formed on the gate insulating film of the capacitor, and extraction electrode regions formed to interpose a body region of the capacitor provided under the gate electrode of the capacitor in the surface of the semiconductor substrate.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P? pocket regions 17 and N? pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P? pocket regions 17 and the N? pocket regions 27.

Abstract: A plurality of ONO films are provided in a matrix on a substrate surface. Gate electrodes are provided on each of the ONO films. Further provided in the substrate surface are n-type impurity layers and p-type impurity layers. Each of the p-type impurity layers is arranged between the n-type impurity layers. In a plan view of the substrate surface, the n-type impurity layers and the p-type impurity layers are arranged to surround the respective ONO films and the gate electrodes.

Abstract: It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.

Abstract: A plurality of ONO films (30) are provided in a matrix on a substrate surface (20S). Gate electrodes are provided on each of the ONO films (30). Further provided in the substrate surface (20S) are n-type impurity layers (50) and p-type impurity layers (60). Each of the p-type impurity layers (60) is arranged between the n-type impurity layers (50). In a plan view of the substrate surface (20S), the n-type impurity layers (50) and the p-type impurity layers (60) are arranged to surround the respective ONO films (30) and the gate electrodes.