Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

Abstract: According to one embodiment, a display device includes a lower electrode, a partition which has a conductive lower portion and an upper portion provided on the lower portion and protruding from a side surface of the lower portion, an organic layer provided on the lower electrode, and an upper electrode provided on the organic layer. The organic layer has a hole injection layer spaced apart from the partition, a first intermediate layer including a first light emitting layer, a first charge generation layer spaced apart from the partition, and a second intermediate layer including a second light emitting layer. The hole injection layer and the first charge generation layer are spaced apart from each other and are further spaced apart from the upper electrode.

Abstract: A load adjusting system includes: a bevel grinding device including a grinding head configured to grind a bevel part of a substrate; and a control device, the control device is configured to: acquire, from a load measuring device that performs measurement of a pressing load applied from the grinding head, measurement data acquired by performing the measurement; calculate, based on the measurement data and based on a set parameter set for the grinding head, an adjustment value used for adjusting the pressing load; and control a pressing operation of the grinding head based on the adjustment value.

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

Abstract: A semiconductor memory device comprises a first chip and a second chip bonded via bonding electrodes. The first chip comprises a semiconductor substrate. The second chip comprises: first conductive layers; semiconductor layers facing the first conductive layers; a first wiring layer including bit lines; a second wiring layer including wirings; and a third wiring layer including first bonding electrodes. The wirings each comprise: a first portion provided in a region overlapping one of the bit lines, and is electrically connected to the one of the bit lines; and a second portion provided in a region overlapping one of the first bonding electrodes, and is connected to the one of the first bonding electrodes. At least some of these wirings comprise a third portion connected to one end portion in a second direction of the first portion and one end portion in the second direction of the second portion.

Abstract: A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.

Abstract: A substrate processing apparatus for processing a substrate includes a setting device that sets a plurality of recipe items including operation conditions of the substrate processing apparatus and a recipe generating device that acquires a plurality of recipe models obtained by changing values of the plurality of recipe items and experimenting or simulating a processing result of the substrate and analyzes the plurality of recipe models to generate a recipe, the recipe generating device combining a part or all of the plurality of recipe models to generate the recipe such that a calculation value of a processing result of the substrate by the recipe satisfies a predetermined condition.

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

Abstract: A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.

Abstract: A substrate processing apparatus which causes a processing tape to abut against a processing object, including: a tape supply reel configured to supply the processing tape; a tape recovery reel configured to recover the processing tape; a recovery motor configured to apply a torque to the tape recovery reel; a tape feed motor configured to feed the processing tape between the tape supply reel and the tape recovery reel; and a control unit configured to control the tape feed motor, wherein the control unit controls the torque of the recovery motor depending on a change in an outer diameter of a roll of the processing tape wound by the tape recovery reel such that tension applied to the processing tape is constant, using a feed length of the tape fed by the tape feed motor and a thickness of the processing tape.

Abstract: A semiconductor memory device includes first and second wirings extending in a first direction and spaced apart from each other in the first direction, third wirings above the first and second wirings and extending in a second direction, fourth and fifth wirings above the third wirings, extending in the first direction, and spaced apart from each other in the second direction, a plurality of memory cells between each third wiring and each of first, second, fourth, and fifth wirings, voltage application circuits, connection conductors between the voltage application circuits and the wirings, and connection wirings that electrically connect the fourth and fifth wirings to the voltage application circuits. The voltage application circuits are arranged so that a non-selected voltage application circuit is under a space between the first and second wirings, and a selected voltage application circuit is under the first wiring.

Abstract: A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. The switching element of the first memory cell includes a gate coupled to the third wiring. The switching elements of the second and third memory cells each include a gate coupled to the fourth wiring. The variable resistance elements of the first to third memory cells are formed with equal distances from each other.

Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.

Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.

Abstract: A semiconductor memory device includes first and second wirings extending in a first direction and spaced apart from each other in the first direction, third wirings above the first and second wirings and extending in a second direction, fourth and fifth wirings above the third wirings, extending in the first direction, and spaced apart from each other in the second direction, a plurality of memory cells between each third wiring and each of first, second, fourth, and fifth wirings, voltage application circuits, connection conductors between the voltage application circuits and the wirings, and connection wirings that electrically connect the fourth and fifth wirings to the voltage application circuits. The voltage application circuits are arranged so that a non-selected voltage application circuit is under a space between the first and second wirings, and a selected voltage application circuit is under the first wiring.

Abstract: A current measuring module for measuring a current flowing through the substrate holder using an inspection substrate is provided. The substrate holder includes a plurality of holder electric contacts. The plurality of holder electric contacts contact a substrate to supply the held substrate with a current. The substrate holder holds the inspection substrate for measuring the current flowing through the substrate holder. The plurality of holder electric contacts contact a plurality of respective independent substrate electric contacts disposed on the inspection substrate. The inspection substrate includes a plurality of measurement points connected to the plurality of respective substrate electric contacts with wirings and substrate side connectors electrically connected to the plurality of measurement points. The current measuring module includes a plurality of inspection probes configured to contact the plurality of respective measurement points on the inspection substrate.

Abstract: A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. The switching element of the first memory cell includes a gate coupled to the third wiring. The switching elements of the second and third memory cells each include a gate coupled to the fourth wiring. The variable resistance elements of the first to third memory cells are formed with equal distances from each other.

Abstract: A semiconductor storage device includes a global bit line extending in a horizontal direction, a select transistor provided on the global bit line and including a first terminal connected to the global bit line, a bit line provided on the select transistor, extending in a vertical direction, and connected to a second terminal of the select transistor, a plurality of word lines and insulating layers that are stacked alternately in a vertical direction, a first variable resistance layer between one of the plurality of word lines and a first side surface of the bit line, a plurality of dummy word lines and insulating layers that are stacked alternately in the vertical direction and disposed at the same level as the plurality of word lines, and a second variable resistance layer between the plurality of dummy word lines and a second side surface of the bit line.