Patents by Inventor Hiroyuki Tamaru

Hiroyuki Tamaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tester for semiconductor device
    Patent number: 6566899
    Abstract: A connection portion having a plurality of pads is provided on a test board. On the connection portion, a plurality of anisotropic conductive sheets, the sheet for the power source and the sheet for grounding are provided in an alternate manner. The connection portion and the semiconductor device are connected via the anisotropic conductive sheet, the sheet for the power source and the sheet for grounding. When the pin arrangement of the semiconductor device is changed, the sheet for the power source and the sheet for the grounding are changed.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: May 20, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Tamaru, Mitsuo Fujii
  • Tester for semiconductor device
    Publication number: 20030030462
    Abstract: A connection portion having a plurality of pads is provided on a test board. On the connection portion, a plurality of anisotropic conductive sheets, the sheet for the power source and the sheet for grounding are provided in an alternate manner. The connection portion and the semiconductor device are connected via the anisotropic conductive sheet, the sheet for the power source and the sheet for grounding. When the pin arrangement of the semiconductor device is changed, the sheet for the power source and the sheet for the grounding are changed.
    Type: Application
    Filed: September 27, 2002
    Publication date: February 13, 2003
    Inventors: Hiroyuki Tamaru, Mitsuo Fujii
  • Tester for semiconductor device
    Patent number: 6483331
    Abstract: A connection portion having a plurality of pads is provided on a test board. On the connection portion, a plurality of anisotropic conductive sheets, the sheet for the power source and the sheet for grounding are provided in an alternate manner. The connection portion and the semiconductor device are connected via the anisotropic conductive sheet, the sheet for the power source and the sheet for grounding. When the pin arrangement of the semiconductor device is changed, the sheet for the power source and the sheet for the grounding are changed.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: November 19, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Tamaru, Mitsuo Fujii
  • Tester for semiconductor device
    Publication number: 20010026168
    Abstract: A connection portion having a plurality of pads is provided on a test board. On the connection portion, a plurality of anisotropic conductive sheets, the sheet for the power source and the sheet for grounding are provided in an alternate manner. The connection portion and the semiconductor device are connected via the anisotropic conductive sheet, the sheet for the power source and the sheet for grounding. When the pin arrangement of the semiconductor device is changed, the sheet for the power source and the sheet for the grounding are changed.
    Type: Application
    Filed: March 28, 2001
    Publication date: October 4, 2001
    Inventors: Hiroyuki Tamaru, Mitsuo Fujii