Abstract: A semiconductor integrated circuit formed on an insulator substrate and comprising a drive transistor and a load transistor, in which a threshold voltage of the load transistor is set in the range of -2.8V to -1.0V so as to ensure stable operation without temperature dependency with respect to working speed and power consumption of the circuit.

Abstract: In an apparatus for forming a single crystal semiconductor layer from a non-single-crystalline semiconductor material by scanning a region of the material with an electron beam, a first pair of deflection electrodes and a second pair of deflection electrodes, both pairs being provided in the path of the electron beam. A deflection signal generated by modifying the amplitude of a high-frequency fundamental wave signal with a modulation wave signal having a frequency lower than that of the high-frequency fundamental wave signal is supplied to the deflection electrodes of the first pair. The electrodes rapidly deflect the electron beam in a first direction, while changing the range of deflecting the beam, thereby forming a locus of the beam spot on the sample. Simultaneously, the deflection electrodes of the second pair deflect the beam in a second direction, thereby annealing a region of the material, to form a single crystal semiconductor layer.

Abstract: In an apparatus for forming a single crystal semiconductor layer from a non-single-crystalline semiconductor material by scanning a region of the material with an electron beam, a first pair of deflection electrodes and a second pair of deflection electrodes, both pairs being provided in the path of the electron beam. A deflection signal generated by modifying the amplitude of a high-frequency fundamental wave signal with a modulation wave signal having a frequency lower than that of the high-frequency fundamental wave signal is supplied to the deflection electrodes of the first pair. The electrodes rapidly deflect the electron beam in a first direction, while changing the range of deflecting the beam, thereby forming a locus of the beam spot on the sample. Simultaneously, the deflection electrodes of the second pair deflect the beam in a second direction, thereby annealing a region of the material, to form a single crystal semiconductor layer.

Abstract: A semiconductor device having silicon-on-sapphire structure in which a pn junction element is formed in a silicon substrate disposed on a sapphire plate. An oxide layer is formed in the surface area of the p-type region which serves to form the pn junction elements.

Abstract: A MOS integrated circuit comprises a MOS IC body including at least one MOS transistor made of an island-like semiconductor layer formed on an insulating substrate, and a protective circuit connected between a signal input terminal and the gate electrode of a MOS transistor at least at an input stage of the MOS IC body and adapted to protect the MOS integrated circuit against an irregular input signal.

Abstract: An insulated-gate field-effect transistor having improved high-speed operation characteristics and high channel controllability includes a source region having first and second diffused regions and a drain region having first and second diffused regions. The first diffused regions of both the source and drain regions are formed by diffusion of a first impurity having relatively low diffusion coefficient and the second diffused regions of both the source and drain regions are formed by diffusion of a second impurity having relatively high diffusion coefficient.

Abstract: A method for the manufacture of semiconductor devices comprises the steps of forming a number of mutually electrically isolated semiconductor islands on an insulating substrate and cutting a semiconductor wafer, made of semiconductor elements and substrate, along its dicing line to provide a number of semiconductor chips, the method characterized in that additional semiconductor islands are formed on the insulating substrate simultaneously with, or after, the formation of the first-mentioned semi-conductor islands so that each substantially surrounds the chip. The method permits very easy mask alignments for photoengraving as well as a clear judgment as to whether or not the formation of contact openings has been completed.