Patents by Inventor Hiroyuki Taninaka

Hiroyuki Taninaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11970802
    Abstract: The present invention provides a network structure having excellent repeated compression durability, the network structure having a low repeated compression residual strain and a high hardness retention after repeated compression. A network structure comprising a three-dimensional random loop bonded structure obtained by forming random loops with curling treatment of a continuous linear structure including a polyester-based thermoplastic elastomer and having a fineness of not less than 100 dtex and not more than 60000 dtex, and by making each loop mutually contact in a molten state, wherein the network structure has an apparent density of 0.005 g/cm3 to 0.20 g/cm3, a 50%-constant displacement repeated compression residual strain of not more than 15%, and a 50%-compression hardness retention of not less than 85% after 50%-constant displacement repeated compression.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: April 30, 2024
    Assignee: TOYOBO CO., LTD.
    Inventors: Teruyuki Taninaka, Shinichi Kobuchi, Hiroyuki Wakui
  • Patent number: 4831587
    Abstract: A memory associated with an address circuit receiving an address signal to designate a location of the memory to be accessed. The address circuit includes an X-decoder and a Y-decoder associated to the memory, and a multiplexor receiving at least a portion of an address input and adapted to selectively distribute the above portion of the address input to the X-decoder and the Y-decoder. Specifically, the multiplexor receives at least one first bit of a portion of the address signal to be inputted to the X-decoder and at least one second bit of the remaining portion of the address signal to be iputted to the Y-decoder. In a first condition, the multiplexor operates to supply the first bit and the second bit of the address input to the X-decoder and the Y-decoder, respectively. In a second condition, the multiplexor operates to supply the first bit and the second bit of the address input to the Y-decoder and the X-decoder, respectively.
    Type: Grant
    Filed: May 27, 1987
    Date of Patent: May 16, 1989
    Assignee: NEC Corporation
    Inventors: Hiroyuki Taninaka, Mikio Saitou