Patents by Inventor Hiroyuki Tezuka
Hiroyuki Tezuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11970091Abstract: To provide a vehicle seat in which the rotation device is disposed without compromising the passenger comfort in the cabin, a vehicle seat includes: a floor panel which has a sheet shape, constitutes a floor surface of a cabin, and has an elongated hole extending linearly; a slide device provided below the floor panel to be slidable along the elongated hole; a rotation device provided on the slide device to be rotatable about a rotation axis below the floor panel, the rotation axis extending vertically and overlapping with the elongated hole; a support leg which is columnar in shape, is provided on the rotation device along the rotation axis, and extends to above the floor panel by passing through the elongated hole; and a seat main body which is joined to an upper end of the support leg and on which an occupant can be seated.Type: GrantFiled: March 25, 2020Date of Patent: April 30, 2024Assignee: TS TECH CO., LTD.Inventors: Hiroyuki Numajiri, Nobuyuki Tezuka, Akihito Kobayashi, Tadashi So, Akira Miyoshi, Tomoyuki Kurimoto
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Publication number: 20240038286Abstract: A leakage current of a MOS transistor that performs writing is reduced. The resistance change memory includes a memory cell, a write drive unit, a write control unit, and a well potential adjustment unit. The memory cell includes a resistance change element. The write drive unit applies a write voltage to the memory cell to perform writing of data. The write control unit outputs a write control signal for controlling the writing to the write drive unit. The well potential adjustment unit adjusts a well potential of a well region in which an element constituting the write drive unit is arranged according to the write voltage at time of the writing.Type: ApplicationFiled: December 16, 2021Publication date: February 1, 2024Inventors: HARUKO TAKAHASHI, MASAMI KURODA, HIROYUKI TEZUKA
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Publication number: 20230419144Abstract: A quantum computation unit, a classical computation unit, and a management unit are provided to learn distribution of a quantum dataset. A structure of a generator is determined from multiple samples of latent variables and values of quantum circuit parameters. A ground cost and a gradient of the ground cost are calculated from the generator and the quantum dataset. An optimal transport loss and a gradient of the optimal transport loss are calculated using the ground cost and the gradient of the ground cost. An updating process is executed that updates the quantum circuit parameter using the gradient of the optimum transport loss, thereby reducing the optimum transport loss. The updating process is repeated until the optimum transport loss converges.Type: ApplicationFiled: June 21, 2023Publication date: December 28, 2023Inventors: Shumpei UNO, Hiroyuki TEZUKA
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Publication number: 20220399049Abstract: A standard potential used for reading is set flexibly according to the state of a storage device. A data memory cell group stores data. A reference memory cell group stores a plurality of reference potentials. A standard potential generating section selects a prescribed number of reference potentials from among the plurality of reference potentials stored in the reference memory cell group and generates the standard potential. A reference potential selection control section controls the selection by the standard potential generating section according to prescribed conditions. A sense amplifier amplifies data read out from the data memory cell group, by using the standard potential as a standard.Type: ApplicationFiled: September 29, 2020Publication date: December 15, 2022Inventors: Hiroyuki TEZUKA, Masami KURODA
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Patent number: 11367496Abstract: The reference cells used for reading out data are tested efficiently so as to improve the reliability of the readout data. A memory circuit includes multiple memory arrays, a selection circuit, and a sense amplifier. The selection circuit selects values output from memory cells in any of the multiple memory arrays so as to supply a first value and a second value. A sense amplifier has a first input terminal and a second input terminal. The sense amplifier amplifies and outputs the first value supplied to the first input terminal in reference to the second value supplied to the second input terminal.Type: GrantFiled: July 25, 2019Date of Patent: June 21, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroyuki Tezuka, Masami Kuroda
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Patent number: 11315616Abstract: To provide a control circuit capable of not only suppressing an increase in power consumption with a simple configuration but also preventing erroneous writing and destruction of a memory element. Provided is a control circuit that outputs a signal for discharging charges accumulated in a source line and a bit line according to activation of a word line, and outputs a signal for making the source line and the bit line be in a floating state by a start of writing or reading, with respect to a memory cell including the source line, the bit line, a transistor that is provided between the source line and the bit line, and switches on and off by a potential of the word line, and a memory element connected to the transistor in series.Type: GrantFiled: February 14, 2018Date of Patent: April 26, 2022Assignee: Sony Semiconductor Solutions CorporationInventor: Hiroyuki Tezuka
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Publication number: 20210280265Abstract: The reference cells used for reading out data are tested efficiently so as to improve the reliability of the readout data. A memory circuit includes multiple memory arrays, a selection circuit, and a sense amplifier. The selection circuit selects values output from memory cells in any of the multiple memory arrays so as to supply a first value and a second value. A sense amplifier has a first input terminal and a second input terminal. The sense amplifier amplifies and outputs the first value supplied to the first input terminal in reference to the second value supplied to the second input terminal.Type: ApplicationFiled: July 25, 2019Publication date: September 9, 2021Inventors: HIROYUKI TEZUKA, MASAMI KURODA
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Patent number: 11087813Abstract: A control circuit capable of generating a reliable reference potential while suppressing increase in power consumption and cost. A control circuit causes write processing to be performed individually for a first reference element set to a first resistance state in generating a reference potential used for reading data from a memory element, and a second reference element different from the first reference element, the second reference element being set to a second resistance state different from the first resistance state in generating the reference potential.Type: GrantFiled: February 14, 2018Date of Patent: August 10, 2021Assignee: Sony Semiconductor Solutions CorporationInventor: Hiroyuki Tezuka
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Publication number: 20210134337Abstract: To provide a control circuit capable of not only suppressing an increase in power consumption with a simple configuration but also preventing erroneous writing and destruction of a memory element. Provided is a control circuit that outputs a signal for discharging charges accumulated in a source line and a bit line according to activation of a word line, and outputs a signal for making the source line and the bit line be in a floating state by a start of writing or reading, with respect to a memory cell including the source line, the bit line, a transistor that is provided between the source line and the bit line, and switches on and off by a potential of the word line, and a memory element connected to the transistor in series.Type: ApplicationFiled: February 14, 2018Publication date: May 6, 2021Inventor: Hiroyuki TEZUKA
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Publication number: 20210134338Abstract: To provide a control circuit capable of generating a reliable reference potential while suppressing increase in power consumption and cost. A control circuit causes write processing to be performed individually for a first reference element set to a first resistance state in generating a reference potential used for reading data from a memory element, and a second reference element different from the first reference element, the second reference element being set to a second resistance state different from the first resistance state in generating the reference potential.Type: ApplicationFiled: February 14, 2018Publication date: May 6, 2021Inventor: Hiroyuki TEZUKA
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Patent number: 10971197Abstract: To provide a control circuit capable of reliably generating a reference potential while suppressing increase in power consumption and cost. Provided is a control circuit that performs control to separate from a sense amplifier a second reference element set to a predetermined resistance state, which is different from a first reference element set to a predetermined resistance state and connected to the sense amplifier in generating a reference potential used for data read through the sense amplifier from a memory cell.Type: GrantFiled: February 14, 2018Date of Patent: April 6, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Hiroyuki Tezuka
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Publication number: 20200020366Abstract: To provide a control circuit capable of reliably generating a reference potential while suppressing increase in power consumption and cost. Provided is a control circuit that performs control to separate from a sense amplifier a second reference element set to a predetermined resistance state, which is different from a first reference element set to a predetermined resistance state and connected to the sense amplifier in generating a reference potential used for data read through the sense amplifier from a memory cell.Type: ApplicationFiled: February 14, 2018Publication date: January 16, 2020Inventor: HIROYUKI TEZUKA
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Publication number: 20190053406Abstract: [Object] To reduce electromagnetic noise with ease in a semiconductor device provided with wiring serving as a source of noise. [Solution] The semiconductor device includes first and second substrates. In this semiconductor device, a plurality of first signal lines are wired in a predetermined direction on the first substrate. In addition, in a semiconductor device on which the plurality of first signal lines are wired in the predetermined direction, a second signal line, which produces a plurality of magnetic fields with mutually different directions in a region between two adjacent signal lines of the plurality of first signal lines, is wired on the second substrate.Type: ApplicationFiled: November 14, 2016Publication date: February 14, 2019Inventor: HIROYUKI TEZUKA
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Patent number: 9842645Abstract: A nonvolatile memory device comprises: a nonvolatile memory; a resistance-time converter that outputs an end signal at timing according to a resistance value of the nonvolatile memory; and a time-digital converter that measures the time from input of a start signal to input of the end signal and converts the measured time into a digital value. The time-digital converter includes: a ring delay circuit that includes delay elements connected in a ring configuration; a counter circuit that counts the number of times of a rising edge or a falling edge in output of one of the delay elements; a first memory circuit that stores, based on the end signal, outputs of the delay elements as first data; and a second memory circuit that stores, based on the end signal, a count value of the counter circuit as second data.Type: GrantFiled: March 6, 2017Date of Patent: December 12, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hiroyuki Tezuka, Yoshikazu Katoh
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Publication number: 20170294227Abstract: A nonvolatile memory device comprises: a nonvolatile memory; a resistance-time converter that outputs an end signal at timing according to a resistance value of the nonvolatile memory; and a time-digital converter that measures the time from input of a start signal to input of the end signal and converts the measured time into a digital value. The time-digital converter includes: a ring delay circuit that includes delay elements connected in a ring configuration; a counter circuit that counts the number of times of a rising edge or a falling edge in output of one of the delay elements; a first memory circuit that stores, based on the end signal, outputs of the delay elements as first data; and a second memory circuit that stores, based on the end signal, a count value of the counter circuit as second data.Type: ApplicationFiled: March 6, 2017Publication date: October 12, 2017Inventors: HIROYUKI TEZUKA, YOSHIKAZU KATOH
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Patent number: 8897350Abstract: A phase adjuster arranges phases of waveforms of a complex signal after orthogonal transform. An edge detector detects an edge of the complex signal after phase adjustment. A phase shift detector detects phase shift of an output signal of the edge detector between the in-phase signal and the quadrature signal after the orthogonal transform, and outputs a phase error signal (PE). The oscillator connected to mixers and a shifter to perform the orthogonal transform includes a phase adjustment section adjusting an edge of a voltage controlled oscillator (VCO) clock based on the phase error signal (PE) and correcting the phase shift of an original signal.Type: GrantFiled: June 19, 2014Date of Patent: November 25, 2014Assignee: Panasonic CorporationInventors: Hiroki Mouri, Kouichi Nagano, Hiroyuki Tezuka
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Publication number: 20140301516Abstract: A phase adjuster arranges phases of waveforms of a complex signal after orthogonal transform. An edge detector detects an edge of the complex signal after phase adjustment. A phase shift detector detects phase shift of an output signal of the edge detector between the in-phase signal and the quadrature signal after the orthogonal transform, and outputs a phase error signal (PE). The oscillator connected to mixers and a shifter to perform the orthogonal transform includes a phase adjustment section adjusting an edge of a voltage controlled oscillator (VCO) clock based on the phase error signal (PE) and correcting the phase shift of an original signal.Type: ApplicationFiled: June 19, 2014Publication date: October 9, 2014Inventors: Hiroki MOURI, Kouichi NAGANO, Hiroyuki TEZUKA
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Patent number: 6786290Abstract: A straddle-type four wheeled all terrain vehicle includes a bar-type handle provided forward of a straddle-type seat; a vehicle body cover covering a portion of a vehicle body including a steering shaft of the handle, the steering shaft penetrating through the vehicle body cover; and a belt converter, wherein an opening of the vehicle body cover through which the steering shaft pass is an intake port of a cooling air into the belt converter.Type: GrantFiled: February 1, 2002Date of Patent: September 7, 2004Inventors: Yasuhiro Kuji, Yuichi Kawamoto, Takeshi Usui, Hiroyuki Tezuka
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Patent number: 6568497Abstract: In a protective structure for a joint portion of an axle according to the present invention, a knuckle member 24 is provided with a covering portion 28 surrounding a joint portion 23 in the circumferential direction of a constant velocity joint shaft 22, and the joint portion 23 is accommodated in an inner space of the covering portion 28. The knuckle member 24 having a driven shaft support portion 33, a strut support portion 35 and covering portion the is molded out 28 an aluminum alloy into an integral part. According to the present invention, the joint portion is protected reliably by the covering portion, and, a reduction of the weight of the protective structure and simplification of a working process for the production thereof can be attained.Type: GrantFiled: July 7, 2000Date of Patent: May 27, 2003Assignee: Kawasaki Jukogyo Kabushiki KaishaInventors: Hiroyuki Tezuka, Sosuke Kinouchi, Fumio Mizuta
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Publication number: 20020108795Abstract: A straddle-type four wheeled all terrain vehicle comprises: a bar-type handle provided forward of a straddle-type seat; a vehicle body cover covering a portion of a vehicle body including a steering shaft of the handle, the steering shaft penetrating through the vehicle body cover; and a belt converter, wherein an opening of the vehicle body cover through which the steering shaft pass is an intake port of a cooling air into the belt converter.Type: ApplicationFiled: February 1, 2002Publication date: August 15, 2002Inventors: Yasuhiro Kuji, Yuichi Kawamoto, Takeshi Usui, Hiroyuki Tezuka