Patents by Inventor Hiroyuki Tomimatsu

Hiroyuki Tomimatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240066875
    Abstract: A liquid ejection apparatus includes an ejection unit including a first ejection unit having a first nozzle surface in which a first nozzle is opened, the first ejection unit being configured to eject a first liquid from the first nozzle onto a medium, and a second ejection unit having a second nozzle surface in which a second nozzle is opened, the second ejection unit being configured to eject a second liquid from the second nozzle onto a medium, the second liquid containing a component for coagulating the first liquid, a detection unit configured to detect contact between the ejection unit and a medium, and a notification unit configured to perform notification of information for prompting confirmation of the first nozzle surface and the second nozzle surface when the detection unit detects contact between the ejection unit and a medium.
    Type: Application
    Filed: August 29, 2023
    Publication date: February 29, 2024
    Inventor: Hiroyuki TOMIMATSU
  • Publication number: 20230294409
    Abstract: A liquid ejection device includes a liquid ejection portion including a plurality of first nozzles configured to eject a first liquid containing an inorganic pigment and a plurality of second nozzles configured to eject a second liquid not containing a substance having a hardness the same as or higher than a hardness of the inorganic pigment contained in the first liquid, and a control portion, wherein the control portion performs the cleaning such that a proportion of the inorganic pigment of the first liquid in a mixed liquid, remaining on the nozzle surface, containing the first liquid and the second liquid is smaller than a proportion of the inorganic pigment in the first liquid, and then performs wiping of the nozzle surface.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 21, 2023
    Inventor: Hiroyuki TOMIMATSU
  • Patent number: 9050800
    Abstract: A liquid ejecting head comprises a pressure generation chamber communicating with a nozzle opening, a vibrating wall provided as one surface of the pressure generation chamber and vibrates so that ejects the liquid from the nozzle opening, and a resin portion having a recessed arc-shape and formed in a corner of the pressure generation chamber and formed of a resin material having a Young's modulus of less than or equal to 10 GPa. A ratio r/w of a radius r of the surface of the resin portion to a width w of the pressure generation chamber defined by the vibrating wall is greater than or equal to 0.017 and less than or equal to 0.087.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: June 9, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Hiroshi Ito, Yasumi Ikehara, Jiro Kato, Hiroyuki Tomimatsu
  • Patent number: 8998389
    Abstract: A liquid ejecting head comprises a pressure generation chamber communicating with a nozzle opening, a vibrating wall provided as one surface of the pressure generation chamber and vibrates so that ejects the liquid from the nozzle opening, and a resin portion having a recessed arc-shape and formed in a corner of the pressure generation chamber and formed of a resin material having a Young's modulus of less than or equal to 10 GPa. A ratio r/w of a radius r of the surface of the resin portion to a width w of the pressure generation chamber defined by the vibrating wall is greater than or equal to 0.017 and less than or equal to 0.087.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: April 7, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Hiroshi Ito, Yasumi Ikehara, Jiro Kato, Hiroyuki Tomimatsu
  • Publication number: 20140002550
    Abstract: A liquid ejecting head comprises a pressure generation chamber communicating with a nozzle opening, a vibrating wall provided as one surface of the pressure generation chamber and vibrates so that ejects the liquid from the nozzle opening, and a resin portion having a recessed arc-shape and formed in a corner of the pressure generation chamber and formed of a resin material having a Young's modulus of less than or equal to 10 GPa. A ratio r/w of a radius r of the surface of the resin portion to a width w of the pressure generation chamber defined by the vibrating wall is greater than or equal to 0.017 and less than or equal to 0.087.
    Type: Application
    Filed: September 6, 2013
    Publication date: January 2, 2014
    Applicant: Seiko Epson Corporation
    Inventors: Hiroshi ITO, Yasumi Ikehara, Jiro Kato, Hiroyuki Tomimatsu
  • Patent number: 8550602
    Abstract: A liquid ejecting head comprises a pressure generation chamber communicating with a nozzle opening, a vibrating wall provided as one surface of the pressure generation chamber and vibrates so that ejects the liquid from the nozzle opening, and a resin portion having a recessed arc-shape and formed in a corner of the pressure generation chamber and formed of a resin material having a Young's modulus of less than or equal to 10 GPa. A ratio r/w of a radius r of the surface of the resin portion to a width w of the pressure generation chamber defined by the vibrating wall is greater than or equal to 0.017 and less than or equal to 0.087.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: October 8, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Hiroshi Ito, Yasumi Ikehara, Jiro Kato, Hiroyuki Tomimatsu
  • Publication number: 20120182360
    Abstract: A liquid ejecting head comprises a pressure generation chamber communicating with a nozzle opening, a vibrating wall provided as one surface of the pressure generation chamber and vibrates so that ejects the liquid from the nozzle opening, and a resin portion having a recessed arc-shape and formed in a corner of the pressure generation chamber and formed of a resin material having a Young's modulus of less than or equal to 10 GPa. A ratio r/w of a radius r of the surface of the resin portion to a width w of the pressure generation chamber defined by the vibrating wall is greater than or equal to 0.017 and less than or equal to 0.087.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 19, 2012
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroshi Ito, Yasumi Ikehara, Jiro Kato, Hiroyuki Tomimatsu
  • Patent number: 7314818
    Abstract: A tip of a first wire is bonded to a first electrode. The first wire is drawn from the first electrode to a bump on a second electrode. A part of the first wire is deformed and bonded to the bump. A tip of a second wire formed in the shape of a ball is bonded to the bump by using a tool in a state in which at least a part of the tip is superposed on the first wire. A part of the first wire which is not deformed by bonding is prevented from being deformed by the tip of the second wire and the tool.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: January 1, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Takuya Takahashi, Hiroyuki Tomimatsu
  • Patent number: 7132738
    Abstract: The invention enhances reliability and achieves higher speeds for semiconductor devices with a stacked structure. A semiconductor device includes a die pad, a plurality of semiconductor chips stacked on one surface of the die pad, leads extending toward the die pad, first wires that are bonded to first pads of a first semiconductor chip among the plurality of semiconductor chips and to second pads of a second semiconductor chip among the plurality of semiconductor chips, second wires that are bonded to the leads and to the first pads or the second pads, and a sealing material that seals the plurality of semiconductor chips and exposes another surface of the die pad.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: November 7, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Tomimatsu
  • Publication number: 20060189117
    Abstract: A tip of a first wire is bonded to a first electrode. The first wire is drawn from the first electrode to a bump on a second electrode. A part of the first wire is deformed and bonded to the bump. A tip of a second wire formed in the shape of a ball is bonded to the bump by using a tool in a state in which at least a part of the tip is superposed on the first wire. A part of the first wire which is not deformed by bonding is prevented from being deformed by the tip of the second wire and the tool.
    Type: Application
    Filed: April 25, 2006
    Publication date: August 24, 2006
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takuya Takahashi, Hiroyuki Tomimatsu
  • Patent number: 7064425
    Abstract: A tip of a first wire is bonded to a first electrode. The first wire is drawn from the first electrode to a bump on a second electrode. A part of the first wire is deformed and bonded to the bump. A tip of a second wire formed in the shape of a ball is bonded to the bump by using a tool in a state in which at least a part of the tip is superposed on the first wire. A part of the first wire which is not deformed by bonding is prevented from being deformed by the tip of the second wire and the tool.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: June 20, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Takuya Takahashi, Hiroyuki Tomimatsu
  • Patent number: 6933172
    Abstract: The invention provides a method for forming spacers very productively. A method for manufacturing a semiconductor wafer includes forming spacers on a plurality of semiconductor chips arranged in a plane on a substrate, respectively. The steps of forming the multiple spacers are conducted collectively on the substrate.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: August 23, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Tomimatsu
  • Publication number: 20040224481
    Abstract: The invention provides semiconductor devices that are excellent in manufacturing efficiency, and provides highly reliable semiconductor devices, circuit substrates and electronic equipment. A method of manufacturing a semiconductor device in accordance with the present invention includes: providing liquid resin on a first semiconductor chip, which is mounted on a substrate having wiring patterns; mounting a second semiconductor chip over the first semiconductor chip through the liquid resin; and hardening the liquid resin to form a spacer between the first semiconductor chip and the second semiconductor chip, and to fix the first and second semiconductor chips together.
    Type: Application
    Filed: February 4, 2004
    Publication date: November 11, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki Tomimatsu
  • Publication number: 20040183170
    Abstract: The invention enhances reliability and achieves higher speeds for semiconductor devices with a stacked structure. A semiconductor device includes a die pad, a plurality of semiconductor chips stacked on one surface of the die pad, leads extending toward the die pad, first wires that are bonded to first pads of a first semiconductor chip among the plurality of semiconductor chips and to second pads of a second semiconductor chip among the plurality of semiconductor chips, second wires that are bonded to the leads and to the first pads or the second pads, and a sealing material that seals the plurality of semiconductor chips and exposes another surface of the die pad.
    Type: Application
    Filed: February 23, 2004
    Publication date: September 23, 2004
    Applicant: Seiko Epson Corporation
    Inventor: Hiroyuki Tomimatsu
  • Patent number: 6770511
    Abstract: The invention realizes preferential routing of wires. A semiconductor device includes leads, a plurality of semiconductor chips stacked in layers, first wires that electrically connect a first semiconductor chip among the plurality of semiconductor chips to the leads, second wires that electrically connect a second semiconductor chip stacked on the first semiconductor chip among the plurality of semiconductor chips to the leads, and first and second bent sections formed in the second wires, each having a curvature greater than other parts thereof. The second wires extend toward the first bent section above the leads, upwardly diagonally extend from the first bent section toward the second semiconductor chip, and downwardly extend from the second bent section to electrically connect to the second semiconductor chip.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: August 3, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Tomimatsu
  • Patent number: 6727574
    Abstract: The invention enhances reliability and achieves higher speeds for semiconductor devices with a stacked structure. A semiconductor device includes a die pad, a plurality of semiconductor chips stacked on one surface of the die pad, leads extending toward the die pad, first wires that are bonded to first pads of a first semiconductor chip among the plurality of semiconductor chips and to second pads of a second semiconductor chip among the plurality of semiconductor chips, second wires that are bonded to the leads and to the first pads or the second pads, and a sealing material that seals the plurality of semiconductor chips and exposes another surface of the die pad.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: April 27, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Hiroyuki Tomimatsu
  • Publication number: 20030207510
    Abstract: The invention realizes preferential routing of wires. A semiconductor device includes leads, a plurality of semiconductor chips stacked in layers, first wires that electrically connect a first semiconductor chip among the plurality of semiconductor chips to the leads, second wires that electrically connect a second semiconductor chip stacked on the first semiconductor chip among the plurality of semiconductor chips to the leads, and first and second bent sections formed in the second wires, each having a curvature greater than other parts thereof. The second wires extend toward the first bent section above the leads, upwardly diagonally extend from the first bent section toward the second semiconductor chip, and downwardly extend from the second bent section to electrically connect to the second semiconductor chip.
    Type: Application
    Filed: February 24, 2003
    Publication date: November 6, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki Tomimatsu
  • Publication number: 20030162324
    Abstract: The invention provides a method for forming spacers very productively. A method for manufacturing a semiconductor wafer includes forming spacers on a plurality of semiconductor chips arranged in a plane on a substrate, respectively. The steps of forming the multiple spacers are conducted collectively on the substrate.
    Type: Application
    Filed: February 24, 2003
    Publication date: August 28, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki Tomimatsu
  • Publication number: 20030155660
    Abstract: A tip of a first wire is bonded to a first electrode. The first wire is drawn from the first electrode to a bump on a second electrode. A part of the first wire is deformed and bonded to the bump. A tip of a second wire formed in the shape of a ball is bonded to the bump by using a tool in a state in which at least a part of the tip is superposed on the first wire. A part of the first wire which is not deformed by bonding is prevented from being deformed by the tip of the second wire and the tool.
    Type: Application
    Filed: January 21, 2003
    Publication date: August 21, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takuya Takahashi, Hiroyuki Tomimatsu
  • Publication number: 20030153124
    Abstract: The invention enhances reliability and achieves higher speeds for semiconductor devices with a stacked structure. A semiconductor device includes a die pad, a plurality of semiconductor chips stacked on one surface of the die pad, leads extending toward the die pad, first wires that are bonded to first pads of a first semiconductor chip among the plurality of semiconductor chips and to second pads of a second semiconductor chip among the plurality of semiconductor chips, second wires that are bonded to the leads and to the first pads or the second pads, and a sealing material that seals the plurality of semiconductor chips and exposes another surface of the die pad.
    Type: Application
    Filed: December 26, 2002
    Publication date: August 14, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Hiroyuki Tomimatsu