Abstract: An interface device and interface device control method that switches a transmission rate to enable high-speed transmission when necessary. In devices (nodes) provided with an interface device, a transmission rate control circuit decreases the frequency of a clock signal to only enable low-speed transmission operations during low-speed transmission and when a transfer operation is not being performed. A node requiring switching to a high-speed transmission rate negotiates with each node included in a route to a transfer destination and reads the device information stored in the register to confirm whether or not each node has a transmission capacity applicable for high-speed transmission. Then, when the transmission capacity is applicable for high-speed transmission, the transmission rate control circuit increases the frequency of the clock signal to change the operating speed of its node and each of the nodes requiring the switching of the transmission rate to high-speed transmission.

Abstract: A packet transfer apparatus for transferring data packets between devices connected to a bus includes a receiving circuit connected to the bus for receiving a packet from the bus and a transmit circuit, also connected to the bus, for forming and placing a transmit packet on the bus. A header identification circuit, connected to the receiving circuit, detects a packet header of the received packet and determines if the packet header indicates a DMA transfer operation. A first buffer is provided for storing the packet data when the packet header indicates a DMA transfer and a second buffer is provided for storing the packet data when the packet header does not indicate a DMA transfer. A memory is connected to the first buffer and stores the packet data it receives from the first buffer. The memory also transfers stored data to the first buffer. A DMA controller is provided to control a DMA operation between the memory and the first buffer.

Abstract: An apparatus and a method for manufacturing granules includes a spray nozzle disposed within a granulating chamber of an apparatus body. The spray nozzle feeds by spraying into the granulating chamber a liquid material comprising at least one of mixture having solid and liquid in a mixed state and solution including solid dissolved therein. An air blowoff portion is provided at a lower region of the granulating chamber for feeding air for floating and fluidizing the liquid material and fine particles under granulation inside the granulating chamber. An air exhaust port is provided at an upper region of the granulating chamber for exhausting the air present inside the granulating chamber. The spray nozzle is designed to spray the liquid material upwardly.

Abstract: An interface circuit having a plug and play function executes a predetermined bus reset sequence in response to a bus reset. During execution, the circuit analyzes relevant data to determine whether an error has occurred. If so, it deletes the information and re-issues the bus reset to re-execute the bus reset sequence. If an error has not occurred, the interface notifies the host controller and supplies it with the relevant data. Because the host controller is notified only if the reset sequence is executed successfully, the application software and the device driver do not process errors. Thus the interface prevents a detected abnormality from affecting the network.

Abstract: An arrangement for stabilizing a horizontal synchronization signal, serving as an input signal for a phase-locked loop (PLL) for generating a clock signal, by separating the horizontal synchronization signal from a composite synchronization signal including both horizontal and vertical synchronization signals. A horizontal synchronization gate signal is generated for outputting a pulse signal approximately in phase with the horizontal synchronization signal and having at least the pulse width of the horizontal synchronization signal in accordance with the composite synchronization signal and a clock pulse signal having a predetermined frequency. The horizontal synchronization signal is retrieved from the composite synchronization signal in accordance with a logical product when matching the polarity of the horizontal synchronization gate signal with the polarity of the composite synchronization signal.