Patents by Inventor Hiroyuki Ujiie

Hiroyuki Ujiie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020018324
    Abstract: A ferromagnetic tunneling magneto-resistive head includes a first yoke, divided into a proximal portion and a distal portion across a gap; a second yoke formed so as to resist the first yoke, positioned opposite a magnetic recording medium, a read head gap being formed between the first and second yokes; a tunneling magneto-resistive element including at least one layer of insulating material, the insulating layer being sandwiched between at least two layers of magnetic material, the tunneling magneto-resistive element magneto-electrically converting a signal magnetic field applied via the first yoke and the second yoke by the recording medium making sliding contact with the read head gap; and a pair of electrodes positioned one at each end of the tunneling magneto-resistive element in a direction of layering of the magnetic layers.
    Type: Application
    Filed: June 1, 2001
    Publication date: February 14, 2002
    Inventors: Kenji Machida, Naoto Hayashi, Kazutoshi Mutou, Toshihiro Uehara, Morio Kondo, Norio Hasegawa, Hiroyuki Ujiie, Akira Nakamura
  • Patent number: 5946310
    Abstract: A processor bus PBS connecting each LSI and a micro processor has been removed in an asynchronous transfer mode ATM switch in order to reduce number of contact terminals for LSIs, which are employed to constitute the asynchronous transfer mode ATM switch.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: August 31, 1999
    Assignee: Fujitsu Limited
    Inventor: Hiroyuki Ujiie
  • Patent number: 5311518
    Abstract: An ISDN interface circuit is provided which is coupled to a terminal device via a transmission line and a reception line, the transmission line being formed of a pair of first and second wires, and the reception line being formed of a pair of third and fourth wires. The ISDN interface circuit includes a first resistor and a second resistor connected in series at a first node and between the first and second wires of the transmission line, and a third resistor and a fourth resistor connected in series at a second node and between the third and fourth wires of the reception line. The ISDN interface circuit also includes a D.C. power source connected to one of the first node, at which the first resistor and the second resistor are mutually connected in series and the second node, at which the third resistor and the fourth resistor are mutually connected in series. One of the first node and the second node, other than the above-mentioned one of the first node and the second node connected to the D.C.
    Type: Grant
    Filed: April 12, 1991
    Date of Patent: May 10, 1994
    Assignee: Fujitsu Limited
    Inventors: Kenji Takato, Yozo Iketani, Takashi Sato, Hiroyuki Ujiie, Seiji Miyoshi