Abstract: Provided is an image projection device that carries out high precision gesture detection. An image projection device has a projection unit that optically projects image and a gesture detection unit that detects human gestures and generates a signal for operating the projected image on the basis of the detection results. The gesture detection unit controls a range for detecting gesture according to the direction that the projection unit projects light and/or the placement state of the image projection device. The device has a laser light source and photodiode for detecting gestures, or has a pyroelectric sensor for detecting infrared rays.

Abstract: A projection-type video display device which is easily radio-connected to a portable terminal and can freely switchably display video images sent from a plurality of portable terminals is provided. The projection-type video display device is directly connected to a portable terminal (2) by a radio transmission scheme without a relay station. The projection-type video display device (1) has a proximity communication unit (10) which transmits/receives device information of the projection-type display device (1) to/from the portable terminal, and the portable terminal (2) is put over or touched on the proximity communication unit (10) to transmit/receive the device information. The projection-type video display device has a radio signal input unit 20 which selects a desired portable terminal from the plurality of portable terminals and connects the selected portable terminal.

Abstract: In an image projection device in which a projected image can be controlled or operated by gesture, the responsiveness (operability) and/or the usability are improved. The image projection device includes a sensor element to detect a gesture and a control section to generated an operation signal to control (for example, to scroll images or to feed image frames) a projected image projected according to a gesture detected by the sensor element, wherein the control section generates the operation signal when the sensor element detects a gesture in a first direction parallel to the projection surface of the projected image, and when the sensor element detects a gesture in a second direction perpendicular to the projection surface, the control section suspends generation of the operation signal.

Abstract: A phase shifter is provided to adjust the phase of the pixel clock generated by a PLL to the data of the digital image signal regenerated by a digital interface receiver circuit. The pixel clock which is output from the phase shifter is used as a pixel clock in a digital interface transmitter circuit.

Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.

Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.

Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an AID converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of White-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.

Abstract: A video signal processor for outputting a video signal based on an output horizontal synchronizing signal and an output vertical synchronizing signal. The processor includes a circuit inputting a reference horizontal synchronizing signal, a circuit inputting a reference vertical synchronizing signal, a circuit generating an output horizontal synchronizing signal having a frequency different from that of the reference horizontal synchronizing signal, and a circuit generating an output vertical synchronizing signal synchronized in phase with the reference vertical synchronizing signal.

Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.

Abstract: A video signal processor which includes a circuit for converting the number of lines in a digitized video signal, a circuit for generating a display dot clock, a circuit for outputting analog pixel data subjected to a line number conversion and having a frequency different from that of the display dot clock, and a circuit for smoothing the analog pixel data; and in which a frequency fck of the display dot clock, an output frequency frk of the analog pixel data and a frequency fho of the horizontal synchronization signal satisfies an equation;frck/N=fck/M=fhowhere M and N are natural numbers satisfying M.noteq.N.

Abstract: A video display system that includes a housing has arranged thereon a plurality of video input terminals for receiving a plurality of video signals having different scanning frequencies. An expansion/compression processing circuit replaceably mounted on the housing receives and expands/compresses the plurality of video signals and produces at least one video signal expanded/compressed in synchronism with a sync signal selected by a sync switching circuit. At least one of the video signals is synthesized with another video signal, and the synthesized video signal is produced by a video signal synthesis circuit. A video signal from the video signal synthesis circuit is used to generate a video display signal in synchronism with the sync signal. This video display signal is applied to a display. At least one such video display system, an AV controller, a central control console and a lecture table are combined to realize a screen display system.

Abstract: In order to enable sampling of high definition still video signals in addition to common video signals, a function is added for sampling video signals with every other plurality of picture elements as an interval to an image processing apparatus without using a sampling circuit which requires high speed operations. The invention is also intended to change over between two circuits that is, a circuit for using a picture element clock regenerated by a PLL circuit as a sampling clock for analog to digital converters and a circuit for using a clock obtained by dividing the picture element clock as a sampling clock for the analog to digital converters to sample video signals with every other plurality of picture elements as an interval. Thus, it is possible to carry out sampling of high definition video signals with high frequencies in addition to common video signals without necessity of raising the operating speed of the sampling circuit.