Patents by Inventor Hiroyuki Usui

Hiroyuki Usui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9789674
    Abstract: A bonding device for charging a liquid material into a space between plate-shaped members for bonding them together in situ, in which the liquid material may be prevented from exuding from the space between the plate-shaped members. The bonding device includes pair retaining base members for retaining the pair plate-shaped members facing each other, and a retaining base member movement unit for causing movement of the retaining base members towards and away from each other. The bonding device also includes an illumination unit that illuminates curing light to a photo-curable liquid material charged between the pair plate-shaped members held by the pair retaining base members, and a sensor that detects the wetting spreading state of the liquid material charged between the pair plate-shaped members.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: October 17, 2017
    Assignee: Dexerials Corporation
    Inventors: Hiroyuki Usui, Yoshihisa Shinya, Yasumi Endo
  • Publication number: 20170255577
    Abstract: A data transfer apparatus according to an embodiment includes: a first main memory configured to store first data to be used by a first processor; a first hash table in which a hash value and address information of the first data stored in the first main memory are registered; and a data transfer unit configured to transfer data having a hash value not registered in the first hash table from among second data stored in a second main memory from the second main memory to the first main memory.
    Type: Application
    Filed: September 21, 2016
    Publication date: September 7, 2017
    Inventors: Seiji Maeda, Hiroyuki Usui
  • Publication number: 20170255562
    Abstract: According to an embodiment, a cache device has a data memory capable of storing a piece of first cache line data and a piece of second cache line data for first and second ways in compressed form, and a tag memory configured to store, for each of the pieces of cache line data, a piece of tag data including a piece of uncompressed data writing state information, an absence flag, and a compression information field.
    Type: Application
    Filed: September 19, 2016
    Publication date: September 7, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki USUI, Seiji MAEDA
  • Patent number: 9483442
    Abstract: According to an embodiment, a matrix operation apparatus executing a matrix operation includes multiple nodes, the nodes including: a multiplier configured to perform a first operation for a first input, which is column data and a second input which is row data for the matrix operation and output element components of an operation result of the matrix operation; and an accumulator configured to perform cumulative addition of operation results of the multiplier.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: November 1, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiji Maeda, Hiroyuki Usui
  • Patent number: 9365001
    Abstract: A thermally conductive sheet has cut surfaces with low surface roughness and hence shows reduced thermal resistance at the interfaces, and high thermal conductivity in the thickness direction. Thus, the thermally conductive sheet can be interposed between any of various heat sources and a radiation member. The process for producing the thermally conductive sheet includes at least: an extrusion molding step in which a thermally conductive composition containing a polymer, an anisotropic thermally conductive filler, and a filler is extruded with an extruder to thereby mold an extrusion-molded product in which the anisotropic thermally conductive filler has been oriented along the extrusion direction; a curing step in which the extrusion-molded product is cured to obtain a cured object; and a slicing step in which the cured object is sliced into a given thickness with an ultrasonic cutter in the direction perpendicular to the extrusion direction.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: June 14, 2016
    Assignee: DEXERIALS CORPORATION
    Inventors: Hiroyuki Usui, Keisuke Aramaki
  • Patent number: 9350011
    Abstract: This secondary battery negative electrode material constitutes an active material layer formed on a current collector layer of a secondary battery negative electrode and includes a Si particle and a coating material containing Ni and P, formed to cover a surface of the Si particle.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: May 24, 2016
    Assignees: HITACHI METALS, LTD., TOTTORI UNIVERSITY
    Inventors: Hiroki Sakaguchi, Hiroyuki Usui, Ryouji Inoue, Setsuo Andoh, Ken Asada
  • Patent number: 9308695
    Abstract: A thermally conductive sheet has cut surfaces with low surface roughness and hence shows reduced thermal resistance at the interfaces, and high thermal conductivity in the thickness direction. Thus, the thermally conductive sheet can be interposed between any of various heat sources and a radiation member. The process for producing the thermally conductive sheet includes at least: an extrusion molding step in which a thermally conductive composition containing a polymer, an anisotropic thermally conductive filler, and a filler is extruded with an extruder to thereby mold an extrusion-molded product in which the anisotropic thermally conductive filler has been oriented along the extrusion direction; a curing step in which the extrusion-molded product is cured to obtain a cured object; and a slicing step in which the cured object is sliced into a given thickness with an ultrasonic cutter in the direction perpendicular to the extrusion direction.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: April 12, 2016
    Assignee: DEXERIALS CORPORATION
    Inventors: Hiroyuki Usui, Keisuke Aramaki
  • Patent number: 9223680
    Abstract: An information processing apparatus includes a system memory, a cache system that includes a cache memory, and a plurality of cores, each of which accesses the system memory and the cache memory. The cache system stores in a cache line of the cache memory a break indicator that designates one or more of the plurality of cores. The cache system determine whether a first core in the plurality of cores that issues a request to read data from an address that corresponds to the cache line in which the break indicator is stored matches one of the cores designated by the break indicator. If the first core matches one of the cores designated by the break indicator, the cache system returns a break command to the first core. If the first core does not match one of the cores designated by the break indicator, the cache system returns the data to the first core.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: December 29, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Usui
  • Publication number: 20150261675
    Abstract: An information processing device of an embodiment has an input unit, a storage unit, a read control unit, and a write control unit. A read request and a write request are input to the input unit. The storage unit stores management information. When the read request is input, the read control unit reads read data including the management information from the storage unit, references the management information, and outputs only non-zero data included in a predetermined range of a block row. The write control unit writes only non-zero data to the storage unit and updates the management information immediately before a start position of the continuous non-zero data started from a largest position in the continuous non-zero data started from a position smaller than the predetermined range, a last management information stored in the predetermined range, and the last management information in the predetermined range.
    Type: Application
    Filed: September 11, 2014
    Publication date: September 17, 2015
    Inventors: Hiroyuki USUI, Seiji MAEDA
  • Patent number: 9063915
    Abstract: A microprocessor has a plurality of debug modules, multiple sets of processor cores provided corresponding to the debug modules so that each set of the processor cores are debugged by the corresponding debug module, and a plurality of debug ring units provided corresponding to the debug modules, each debug ring unit generating a debug ring signal for instructing the corresponding processor cores to transit to a debug mode. The debug ring units are connected to generate a ring and sequentially transmit the debug ring signal, and when receiving the debug ring signal, each debug ring unit outputs, to the corresponding debug module, a debug transition signal for instructing the corresponding processor cores to transit to the debug mode.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: June 23, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki Usui
  • Publication number: 20150111103
    Abstract: Provided are an anode active material for lithium ion rechargeable batteries and an anode, which are capable, when used in a lithium ion rechargeable battery, of providing excellent charge/discharge capacity and cycle characteristics, and also high rate performance, as well as a lithium ion rechargeable battery using the same. The anode active material contains particles having a crystal phase represented by RAx, wherein R is at least one element selected from the group consisting of rare earth elements including Sc and Y but excluding La, A is Si and/or Ge, and x satisfies 1.0?x?2.0, and a crystal phase consisting of A. The material is thus useful as an anode material for lithium ion rechargeable batteries.
    Type: Application
    Filed: May 10, 2013
    Publication date: April 23, 2015
    Applicant: SANTOKU CORPORATION
    Inventors: Hiroki Sakaguchi, Hiroyuki Usui, Tadatoshi Murota, Masatoshi Kusatsu
  • Publication number: 20150081752
    Abstract: According to an embodiment, a matrix operation apparatus executing a matrix operation includes multiple nodes, the nodes including: a multiplier configured to perform a first operation for a first input, which is column data and a second input which is row data for the matrix operation and output element components of an operation result of the matrix operation; and an accumulator configured to perform cumulative addition of operation results of the multiplier.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiji Maeda, Hiroyuki Usui
  • Patent number: 8959303
    Abstract: According to one embodiment, an information processor includes an operator and an address protector. The address protector includes a register access interface, an address table, and an access determination module. The register access interface is configured to receive address protection information from the operator. The address table is configured to store the received address protection information. The access determination module is configured to determine whether an access to an address specified by the operator is allowable based on the address protection information, and configured to output an interrupt signal to the operator when the access is unallowable.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Usui
  • Publication number: 20140346710
    Abstract: A thermally conductive sheet has cut surfaces with low surface roughness and hence shows reduced thermal resistance at the interfaces, and high thermal conductivity in the thickness direction. Thus, the thermally conductive sheet can be interposed between any of various heat sources and a radiation member. The process for producing the thermally conductive sheet includes at least: an extrusion molding step in which a thermally conductive composition containing a polymer, an anisotropic thermally conductive filler, and a filler is extruded with an extruder to thereby mold an extrusion-molded product in which the anisotropic thermally conductive filler has been oriented along the extrusion direction; a curing step in which the extrusion-molded product is cured to obtain a cured object; and a slicing step in which the cured object is sliced into a given thickness with an ultrasonic cutter in the direction perpendicular to the extrusion direction.
    Type: Application
    Filed: July 3, 2014
    Publication date: November 27, 2014
    Applicant: DEXERIALS CORPORATION
    Inventors: Hiroyuki USUI, Keisuke ARAMAKI
  • Publication number: 20140349067
    Abstract: A thermally conductive sheet has cut surfaces with low surface roughness and hence shows reduced thermal resistance at the interfaces, and high thermal conductivity in the thickness direction. Thus, the thermally conductive sheet can be interposed between any of various heat sources and a radiation member. The process for producing the thermally conductive sheet includes at least: an extrusion molding step in which a thermally conductive composition containing a polymer, an anisotropic thermally conductive filler, and a filler is extruded with an extruder to thereby mold an extrusion-molded product in which the anisotropic thermally conductive filler has been oriented along the extrusion direction; a curing step in which the extrusion-molded product is cured to obtain a cured object; and a slicing step in which the cured object is sliced into a given thickness with an ultrasonic cutter in the direction perpendicular to the extrusion direction.
    Type: Application
    Filed: July 3, 2014
    Publication date: November 27, 2014
    Applicant: DEXERIALS CORPORATION
    Inventors: Hiroyuki USUI, Keisuke ARAMAKI
  • Publication number: 20140289711
    Abstract: An information processing apparatus includes a system memory, a cache system that includes a cache memory, and a plurality of cores, each of which accesses the system memory and the cache memory. The cache system stores in a cache line of the cache memory a break indicator that designates one or more of the plurality of cores. The cache system determine whether a first core in the plurality of cores that issues a request to read data from an address that corresponds to the cache line in which the break indicator is stored matches one of the cores designated by the break indicator. If the first core matches one of the cores designated by the break indicator, the cache system returns a break command to the first core. If the first core does not match one of the cores designated by the break indicator, the cache system returns the data to the first core.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki USUI
  • Publication number: 20140289483
    Abstract: A shared memory controller controls access to a shared memory by a plurality of master devices based on access requests received from the plurality of master devices. The shared memory control unit includes a memory access arbiter that receives a lock reading request to lock a portion of shared memory, a waiting queue that stores the access requests, and a lock transaction controller. The lock transaction controller receives a plurality of access requests after the lock reading request is received by the memory access arbiter. The lock transaction controller stores the access requests in the waiting queue, and receives an unlock writing request to unlock the portion of shared memory. After the portion of shared memory is unlocked, the lock transaction controller releases the access requests from the waiting queue.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Sohichiroh HOSODA, Jun TANABE, Hiroyuki USUI
  • Patent number: 8808607
    Abstract: A thermally conductive sheet has cut surfaces with low surface roughness and hence shows reduced thermal resistance at the interfaces, and high thermal conductivity in the thickness direction. Thus, the thermally conductive sheet can be interposed between any of various heat sources and a radiation member. The process for producing the thermally conductive sheet includes at least: an extrusion molding step in which a thermally conductive composition containing a polymer, an anisotropic thermally conductive filler, and a filler is extruded with an extruder to thereby mold an extrusion-molded product in which the anisotropic thermally conductive filler has been oriented along the extrusion direction; a curing step in which the extrusion-molded product is cured to obtain a cured object; and a slicing step in which the cured object is sliced into a given thickness with an ultrasonic cutter in the direction perpendicular to the extrusion direction.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: August 19, 2014
    Assignee: Dexerials Corporation
    Inventors: Hiroyuki Usui, Keisuke Aramaki
  • Patent number: 8612725
    Abstract: According to one embodiment, each of routers includes: a cache mechanism that stores data transferred to the other routers or processor elements; and a unit that reads out, when an access generated from each of the processor elements is transferred thereto, if target data of the access is stored in the cache mechanism, the data from the cache mechanism and transmits the data to the processor element as a request source.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Tanabe, Hiroyuki Usui
  • Publication number: 20130326203
    Abstract: A microprocessor has a plurality of debug modules, multiple sets of processor cores provided corresponding to the debug modules so that each set of the processor cores are debugged by the corresponding debug module, and a plurality of debug ring units provided corresponding to the debug modules, each debug ring unit generating a debug ring signal for instructing the corresponding processor cores to transit to a debug mode. The debug ring units are connected to generate a ring and sequentially transmit the debug ring signal, and when receiving the debug ring signal, each debug ring unit outputs, to the corresponding debug module, a debug transition signal for instructing the corresponding processor cores to transit to the debug mode.
    Type: Application
    Filed: August 27, 2012
    Publication date: December 5, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroyuki USUI