Abstract: An object of the invention is to provide molded urethane foam pads and vehicle seats that can contribute to the reduction of environmental load and have appropriate impact resilience and hardness and excellent durability with good balance, and also have high comfort.

Abstract: An object of the invention is to provide molded urethane foam pads and vehicle seats that can contribute to the reduction of environmental load and have appropriate impact resilience and hardness and excellent durability with good balance, and also have high comfort.

Abstract: An object of the invention is to provide molded urethane foam pads and vehicle seats that can contribute to the reduction of environmental load and have appropriate impact resilience and hardness and excellent durability with good balance, and also have high comfort.

Abstract: It is an object of the invention to provide a vibration damping and sound absorbing material containing a plant-derived polyol which material largely contributes a decrease of environmental load and has excellent vibration damping and sound absorbing properties, and it is another object of the invention to provide a production process of the material. Specifically, disclosed is a vibration damping and sound absorbing material which is suitably used for cars. A vibration damping and sound absorbing material comprises a polyurethane foam which comprises, as raw materials, a polyol and/or a polymer-dispersed polyol in which polymer fine particles obtainable by polymerizing an unsaturated bond-containing compound are dispersed in a polyol, and water, a catalyst and a polyisocyanate, wherein the polyol comprises (A) a plant-derived polyol produced using a raw material obtainable by a plant.

Abstract: An object of the invention is to provide molded urethane foam pads and vehicle seats that can contribute to the reduction of environmental load and have appropriate impact resilience and hardness and excellent durability with good balance, and also have high comfort.

Abstract: A control apparatus for an internal combustion engine, includes: a fuel injection unit; an ignition unit; a crank angle detection unit; a fuel pump; a booster unit; an ignition discharge unit; and a control unit that controls the fuel injection unit, the ignition unit, and the fuel pump, that ascertains ignition timings based on crank signals output from the crank angle detection unit, and that performs a startup control sequence that is made up of fuel injection processing, voltage boosting processing, ignition processing, and fuel supply processing.

Abstract: Disclosed is a polyurethane resin composition for reaction injection molding, which contains an isocyanate component containing at least one of an alicyclic polyisocyanate and an aralkyl polyisocyanate and a trimer of hexamethylene diisocyanate, and a polyol component.

Abstract: It is an object of the invention to provide a vibration damping and sound absorbing material containing a plant-derived polyol which material largely contributes a decrease of environmental load and has excellent vibration damping and sound absorbing properties, and it is another object of the invention to provide a production process of the material. Specifically, disclosed is a vibration damping and sound absorbing material which is suitably used for cars. A vibration damping and sound absorbing material comprises a polyurethane foam which comprises, as raw materials, a polyol and/or a polymer-dispersed polyol in which polymer fine particles obtainable by polymerizing an unsaturated bond-containing compound are dispersed in a polyol, and water, a catalyst and a polyisocyanate, wherein the polyol comprises (A) a plant-derived polyol produced using a raw material obtainable by a plant.

Abstract: A control apparatus for an internal combustion engine, includes: a fuel injection unit; an ignition unit; a crank angle detection unit; a fuel pump; a booster unit; an ignition discharge unit; and a control unit that controls the fuel injection unit, the ignition unit, and the fuel pump, that ascertains ignition timings based on crank signals output from the crank angle detection unit, and that performs a startup control sequence that is made up of fuel injection processing, voltage boosting processing, ignition processing, and fuel supply processing.

Abstract: A support structure for a pedal of a vehicle pivotablly supports a pedal assembly (34) to a pedal bracket (38) mounted on a vehicle dash panel (6).

Abstract: The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.

Abstract: A cache system includes a plurality of processing units operative to access a main memory device, a plurality of primary caches respectively coupled to the processing units, the primary caches accessible from the processing units at higher speed than the main memory device is accessible from the processing units, and a shared secondary cache coupled to the processing units via the respective primary caches, the shared secondary cache accessible from the processing units at higher speed than the main memory device is accessible from the processing units, wherein the shared secondary cache includes a memory unit configured to store a plurality of entries and, and a set of flags provided separately for each one of the entries, the flags of each set provided in one-to-one correspondence to the processing units, wherein the flags corresponding to a given entry indicate whether the corresponding processing units are using the given entry.

Abstract: A buffer memory temporarily stores data sequentially outputted to a data using apparatus. A memory is accessed by at least one memory access circuit via a bus. A data transfer circuit performs a data transfer from the memory to the buffer memory via the bus. The data transfer circuit performs the data transfer from the memory to the buffer memory under a state where the bus is occupied by the data transfer circuit from when an amount of data in the buffer memory is less than a first predetermined amount to when the amount of data in the buffer memory exceeds a second predetermined amount larger than the first predetermined amount.

Abstract: The processor includes the first through third areas which can be initialized based on an input of the PRST signal. The second and third areas can be initialized based on an input of the HRST signal. The third area can be initialized based on an input of the SRST signal. The first area is not initialized if the second reset signal is generated. The first and second areas are not initialized if the third reset signal is generated. When initialization is to performed, the values of the flags corresponding to each area are referred to. Only those areas whose values of the flags have been reset are initialized.

Abstract: A support structure for a pedal of a vehicle pivotablly supports a pedal assembly (34) to a pedal bracket (38) mounted on a vehicle dash panel (6).

Abstract: The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.

Abstract: The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIS) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.

Abstract: An OR circuit (34, 35) OR-operates an emulator reset signal (106, 107) based on a reset instruction from an emulator (30) and an external reset signal (115, 116) supplied from an external reset generation circuit. The OR operation result is distributed and supplied to a processor (10) and a companion chip (20) as a system reset signal (109, 110), thereby initializing both chips of the processor (10) and the companion chip (20) in accordance with the reset the emulator (30).

Abstract: A microprocessor includes a register and a comparator. The register stores an address area, the address area requiring a guarantee of an access order. The comparator compares an address of the address area held in said register with an address of an address area indicated in an access request from CPU, and outputs a signal to execute an access request succeeding the access request from the CPU after executing an access request preceding the access request from the CPU when the address area indicated in the access request from the CPU matches the address area held in said register.

Abstract: A command fetch control section 1 has an address selection function of selecting the start address of an initialization program stored in a local memory (RAM 6) or an external memory (ROM 9) connected through external buses 7 and 8, based on an address selection signal MS externally given. When a processor 10 in which one or both of the supplies of its internal clocks bck and cck have been stopped after the system wad powered on, is to be restarted, the processor 10 can read out the initialization program necessary for its restarting operation from the high-speed RAM 6. Thus the restarting operation can be performed rapidly.