Patents by Inventor Hiroyuki Yabuki

Hiroyuki Yabuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11187927
    Abstract: A display device according to a present disclosure comprises: a display region; a frame region disposed around the display region; a plurality of first wirings extending in a first direction in the display region; a first drive circuit electrically connected to one end of each of the plurality of first wirings; a first inspection wiring electrically connected to another end of each of the plurality of first wirings through each of a plurality of inspection thin film transistors; a second inspection wiring connected to a gate electrode of each of the plurality of inspection thin film transistors; an inspection drive circuit electrically connected to the second inspection wiring; and an inspection circuit electrically connected to the first inspection wiring, wherein at least a part of the second inspection wiring extends in the first direction in the display region.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 30, 2021
    Assignee: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
    Inventor: Hiroyuki Yabuki
  • Patent number: 10795222
    Abstract: A display device according to a present disclosure comprises: a first glass substrate including a through-hole; a wiring disposed in a first main surface of the first glass substrate; and a terminal formed in a second main surface of the first glass substrate and electrically connected to the wiring through the through-hole.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 6, 2020
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hiroyuki Yabuki, Kazuhiko Tsuda
  • Publication number: 20200166786
    Abstract: A display device according to a present disclosure comprises: a display region; a frame region disposed around the display region; a plurality of first wirings extending in a first direction in the display region; a first drive circuit electrically connected to one end of each of the plurality of first wirings; a first inspection wiring electrically connected to another end of each of the plurality of first wirings through each of a plurality of inspection thin film transistors; a second inspection wiring connected to a gate electrode of each of the plurality of inspection thin film transistors; an inspection drive circuit electrically connected to the second inspection wiring; and an inspection circuit electrically connected to the first inspection wiring, wherein at least a part of the second inspection wiring extends in the first direction in the display region.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 28, 2020
    Inventor: Hiroyuki YABUKI
  • Publication number: 20190271873
    Abstract: A display device according to a present disclosure comprises: a first glass substrate including a through-hole; a wiring disposed in a first main surface of the first glass substrate; and a terminal formed in a second main surface of the first glass substrate and electrically connected to the wiring through the through-hole.
    Type: Application
    Filed: February 26, 2019
    Publication date: September 5, 2019
    Inventors: Hiroyuki YABUKI, Kazuhiko TSUDA
  • Patent number: 10401698
    Abstract: A display device includes a gate lines extending in a first direction, data lines extending in a second direction, pixel electrodes, a common electrode disposed to face the pixel electrodes, common wirings that are electrically connected to the common electrode; and a common bus line that extends in the first direction outside of a display region and is electrically connected to the common wirings. Each of the common wiring includes a first common wiring portion extending in the first direction and a second common wiring portion that is connected to the first common wiring portion and extends in the second direction outside of the display region. A width of the first common wiring portion in the first direction is larger than a width of the second common wiring portion in the first direction. Both ends of the first common wiring portion in the first direction are electrically connected to the common bus line.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: September 3, 2019
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hiroyuki Yabuki, Tomohiro Nakayama
  • Patent number: 10074323
    Abstract: A liquid crystal display device includes an image display area including a plurality of pixels arranged in a matrix, and a peripheral area disposed outside the image display area and including circuitry. The peripheral area includes a first potential supply layer, a second potential supply layer and a third potential supply layer. The first potential supply layer is provided to supply a potential to a common electrode of the plurality of pixels in the image display area. The third potential supply layer is connected to power supply circuitry for receiving the potential. The second potential supply layer includes bridge patterns separated by spaces, and the bridge patterns connect the first potential supply layer and the second potential supply layer.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: September 11, 2018
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Tomohiro Nakayama, Hiroyuki Yabuki, Ryutaro Oke
  • Publication number: 20180239210
    Abstract: A display device includes a gate lines extending in a first direction, data lines extending in a second direction, pixel electrodes, a common electrode disposed to face the pixel electrodes, common wirings that are electrically connected to the common electrode; and a common bus line that extends in the first direction outside of a display region and is electrically connected to the common wirings. Each of the common wiring includes a first common wiring portion extending in the first direction and a second common wiring portion that is connected to the first common wiring portion and extends in the second direction outside of the display region. A width of the first common wiring portion in the first direction is larger than a width of the second common wiring portion in the first direction. Both ends of the first common wiring portion in the first direction are electrically connected to the common bus line.
    Type: Application
    Filed: April 18, 2018
    Publication date: August 23, 2018
    Inventors: Hiroyuki YABUKI, Tomohiro NAKAYAMA
  • Patent number: 9977302
    Abstract: A display device includes a gate lines extending in a first direction, data lines extending in a second direction, pixel electrodes, a common electrode disposed to face the pixel electrodes, common wirings that are electrically connected to the common electrode; and a common bus line that extends in the first direction outside of a display region and is electrically connected to the common wirings. Each of the common wiring includes a first common wiring portion extending in the first direction and a second common wiring portion that is connected to the first common wiring portion and extends in the second direction outside of the display region. A width of the first common wiring portion in the first direction is larger than a width of the second common wiring portion in the first direction. Both ends of the first common wiring portion in the first direction are electrically connected to the common bus line.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 22, 2018
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hiroyuki Yabuki, Tomohiro Nakayama
  • Publication number: 20170131606
    Abstract: A display device includes a gate lines extending in a first direction, data lines extending in a second direction, pixel electrodes, a common electrode disposed to face the pixel electrodes, common wirings that are electrically connected to the common electrode; and a common bus line that extends in the first direction outside of a display region and is electrically connected to the common wirings. Each of the common wiring includes a first common wiring portion extending in the first direction and a second common wiring portion that is connected to the first common wiring portion and extends in the second direction outside of the display region. A width of the first common wiring portion in the first direction is larger than a width of the second common wiring portion in the first direction. Both ends of the first common wiring portion in the first direction are electrically connected to the common bus line.
    Type: Application
    Filed: November 9, 2016
    Publication date: May 11, 2017
    Inventors: Hiroyuki YABUKI, Tomohiro NAKAYAMA
  • Publication number: 20160372062
    Abstract: A liquid crystal display device includes an image display area including a plurality of pixels arranged in a matrix, and a peripheral area disposed outside the image display area and including circuitry. The peripheral area includes a first potential supply layer, a second potential supply layer and a third potential supply layer. The first potential supply layer is provided to supply a potential to a common electrode of the plurality of pixels in the image display area. The third potential supply layer is connected to power supply circuitry for receiving the potential. The second potential supply layer includes bridge patterns separated by spaces, and the bridge patterns connect the first potential supply layer and the second potential supply layer.
    Type: Application
    Filed: June 18, 2015
    Publication date: December 22, 2016
    Inventors: Tomohiro NAKAYAMA, Hiroyuki YABUKI, Ryutaro OKE
  • Publication number: 20160365060
    Abstract: A display device includes gate lines, data lines, pixel electrodes, thin film transistors each of which is disposed near each of intersection portions of the data lines and the gate lines, a slope signal generator and a voltage adjuster. The slope signal generator that generates a slope signal to generate a falling waveform of a gate signal, the slope signal including a first voltage change period and a second voltage change period, the first voltage change period being sloped from a first voltage at which the thin film transistors are put into an on state to a second voltage lower than the first voltage, the second voltage change period being sloped from the second voltage to a third voltage at which the thin film transistors are put into an off state; and the voltage adjuster that adjusts the second voltage.
    Type: Application
    Filed: August 26, 2016
    Publication date: December 15, 2016
    Inventors: Hiroyuki YABUKI, Toshikazu INOUE
  • Patent number: 9500921
    Abstract: In a liquid crystal display device, a TFT substrate includes a GAL layer including gate signal lines, an SDL layer including data signal lines, and a CMT layer including common signal lines and a common signal bus line. The common signal bus line is connected to, among a plurality of common potential supply terminals arranged on one side of the TFT substrate, one of common potential supply terminals that are positioned at both ends, and is connected to a common potential supply terminal on an inner side with respect to the common potential supply terminals at both the ends so as to overlap and cross with at least one of the data signal lines.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: November 22, 2016
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hiroyuki Yabuki, Tomohiro Nakayama
  • Patent number: 9093628
    Abstract: Provided is a liquid crystal display device including a TFT substrate including a pixel electrode and a common electrode. A GAL layer includes gate signal lines, a CMT layer includes common signal lines and a common signal bus line, and an SDL layer includes data signal lines. At least one of the GAL layer and the SDL layer includes a common potential bus line. Further, the TFT substrate includes an interlayer connecting portion for connecting the common signal bus line and the common potential bus line to each other.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: July 28, 2015
    Assignee: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD.
    Inventors: Hiroyuki Yabuki, Tomohiro Nakayama, Yoshihiko Uchida
  • Publication number: 20150177581
    Abstract: In a liquid crystal display device, a TFT substrate includes a GAL layer including gate signal lines, an SDL layer including data signal lines, and a CMT layer including common signal lines and a common signal bus line. The common signal bus line is connected to, among a plurality of common potential supply terminals arranged on one side of the TFT substrate, one of common potential supply terminals that are positioned at both ends, and is connected to a common potential supply terminal on an inner side with respect to the common potential supply terminals at both the ends so as to overlap and cross with at least one of the data signal lines.
    Type: Application
    Filed: March 6, 2014
    Publication date: June 25, 2015
    Applicant: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hiroyuki YABUKI, Tomohiro NAKAYAMA
  • Publication number: 20150171295
    Abstract: Provided is a liquid crystal display device including a TFT substrate including a pixel electrode and a common electrode. A GAL layer includes gate signal lines, a CMT layer includes common signal lines and a common signal bus line, and an SDL layer includes data signal lines. At least one of the GAL layer and the SDL layer includes a common potential bus line. Further, the TFT substrate includes an interlayer connecting portion for connecting the common signal bus line and the common potential bus line to each other.
    Type: Application
    Filed: March 7, 2014
    Publication date: June 18, 2015
    Applicant: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Hiroyuki YABUKI, Tomohiro NAKAYAMA, Yoshihiko UCHIDA
  • Patent number: 7138893
    Abstract: Resonators 4 and 5 are able to oscillate horizontally and vertically to substrate 1. Resonator 4 is primarily composed of a supporting portion in stationary contact with substrate 1, a movable portion including a contact surface making contact with resonator 5 and a contact surface making contact with electrode 7, and a crossing portion that couples the supporting portion and movable portion. Electrode 6 is disposed in the direction in which resonator 5 is spaced apart from resonator 4. Electrode 7 is disposed in the direction in which resonator 4 is spaced apart from resonator 5. Electrode 9 is disposed in a position that causes resonator 5 to generate electrostatic force in a direction different from the direction of both forces of attraction acting between resonators 4 and 5 and between resonator 5 and electrode 6.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: November 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshito Nakanishi, Yoshito Shimizu, Hiroyuki Yabuki
  • Publication number: 20040149558
    Abstract: Resonators 4 and 5 are able to oscillate horizontally and vertically to substrate 1. Resonator 4 is primarily composed of a supporting portion in stationary contact with substrate 1, a movable portion including a contact surface making contact with resonator 5 and a contact surface making contact with electrode 7, and a crossing portion that couples the supporting portion and movable portion. Electrode 6 is disposed in the direction in which resonator 5 is spaced apart from resonator 4. Electrode 7 is disposed in the direction in which resonator 4 is spaced apart from resonator 5. Electrode 9 is disposed in a position that causes resonator 5 to generate electrostatic force in a direction different from the direction of both forces of attraction acting between resonators 4 and 5 and between resonator 5 and electrode 6.
    Type: Application
    Filed: December 3, 2003
    Publication date: August 5, 2004
    Inventors: Yoshito Nakanishi, Yoshito Shimizu, Hiroyuki Yabuki
  • Publication number: 20040032303
    Abstract: In a cross type oscillator (20) comprising spiral inductors (L1, L2) and resonance capacitors (C1, C2) which decide resonance frequencies, transistors (Q1, Q2) which generate negative resistance by base-collector connection with the common emitter, and a current source (I1) which decides a circuit current value, a double-wave output is extracted from the emitter terminals of the transistors (Q1, Q2).
    Type: Application
    Filed: June 24, 2003
    Publication date: February 19, 2004
    Inventors: Nariaki Saito, Yoshito Shimizu, Hiroyuki Yabuki
  • Patent number: 6331804
    Abstract: In a cascade amplifier, the collector of a first transistor with a grounded emitter and the emitter of a second transistor are connected. A third transistor has the base grounded at radio frequency, the emitter connected to the base of the first transistor, and the collector connected to the collector of the second transistor. A fourth transistor connected to the emitter of the third transistor works as a constant current source. A bias changeover circuit supplies base biases of these transisiors. In this constitution, by using the bias changeover circuit for changing over the bias depending on the cut-off condition of the first transistor, the gain is changed over by making either the cascade amplifier or the third transistor operate.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: December 18, 2001
    Assignee: Matsushita Electric Industria, Co., Ltd.
    Inventors: Yoshito Shimizu, Noriaki Saito, Hiroyuki Yabuki
  • Patent number: 6307449
    Abstract: A filter of microwave and millimetric bands with spurious characteristic controlled is disclosed. A filter circuit on a top surface of the substrate including resonators electromagnetically resonating and coupled at a resonance frequency at a microwave band and a millimeter wave band, for filtering an input signal from the connectors through the resonator and outputting the filtered signal through the connector. The filter circuit is contained in a metal box including a top plate confronting the top surface and the filter circuit, side walls, and a bottom plate. An inside surface of the top plate has a shape other than a flat plane to control the spurious characteristic, that is, a protrusion. The bottom plate of the metal box may be coalesced. The spurious characteristic may be controlled by a hollow portion in the top plate. The protruding portion may be provided to the side walls. The spurious frequency may be controlled by a dielectric plate in the space in the shielding.
    Type: Grant
    Filed: July 10, 2000
    Date of Patent: October 23, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Michiaki Matsuo, Hiroyuki Yabuki, Mitsuo Makimoto