Abstract: A contact charging type image forming apparatus, to which only a direct current voltage is applied, includes an electrophotographic photoreceptor that includes a conductive base material A and a photosensitive layer provided on the conductive base material A, and a charging member that includes a conductive base material B and an elastic layer provided on the conductive base material B, in which in a case where a dielectric film thickness of the electrophotographic photoreceptor is defined as L, and a resistance component of an impedance of the charging member in a range of 1 Hz or greater and 500 Hz or less, which is measured by an alternating current impedance method, is defined as R, Expression (1) is satisfied. L<?0.75×loge(R)+15.

Abstract: It has been demanded to improve the poor solubility of curcumin to develop an anti-tumor compound capable of inhibiting the growth of various cancer cells at a low concentration. Thus, disclosed is a novel synthetic compound, a bis(arylmethylidene)acetone, which has both of an excellent anti-tumor activity and a chemo-preventive activity. A bis(arylmethylidene)acetone (i.e., a derivative having a curcumin skeleton) which is an anti-tumor compound and has a chemo-preventive activity is synthesized and screened. A derivative having enhanced anti-tumor activity and chemo-preventive activity can be synthesized.

Abstract: It has been demanded to improve the poor solubility of curcumin to develop an anti-tumor compound capable of inhibiting the growth of various cancer cells at a low concentration. Thus, disclosed is a novel synthetic compound, a bis(arylmethylidene)acetone, which has both of an excellent anti-tumor activity and a chemo-preventive activity. A bis(arylmethylidene)acetone (i.e., a derivative having a curcumin skeleton) which is an anti-tumor compound and has a chemo-preventive activity is synthesized and screened. A derivative having enhanced anti-tumor activity and chemo-preventive activity can be synthesized.

Abstract: In a semiconductor memory device, a plurality of banks is arranged on a semiconductor substrate. A plurality of memory array groups is arranged on the plates. Redundant memory cell array groups replace a memory cell array, including a defective memory cell, and are arranged at every plate. Subword selection circuits switch subword selection lines at every plate. Each of the subword selection circuits has a selection unit which selects a subword selection line on the plate belonging thereto and a redundant subword selection line of the redundant memory cell array arranged on the other adjacent plate.

Abstract: A semiconductor memory includes a block selection circuit, a redundancy main word decoder, a word reset circuit, and a word driver circuit. The block selection circuit outputs a block selection signal based on an address signal. The redundancy main word decoder generates a redundancy main word signal in response to the block selection signal. The word reset circuit outputs a word reset signal in response to the redundancy main word signal. The word driver circuit drives one of word lines in response to the word reset signal, a main word signal indicating selection of the word driver circuit, and a word decode signal indicating selection of the one of word lines.

Abstract: In a semiconductor memory device, a plurality of banks are arranged on a semiconductor substrate. A plurality of plates are arranged. A plurality of memory array groups are arranged on the plates. Redundancy memory cell array groups replace a memory cell array including a defective memory cell and are arranged at every plates. Subword selection circuits switch subword selection lines at every plates. Each of the subword selection circuits has a selection unit which selects a subword selection line on the plate belonging thereto and a redundancy subword selection line of the redundancy memory cell array arranged on the other adjacent plate.

Abstract: A semiconductor memory includes a block selection circuit, a redundancy main word decoder, a word reset circuit, and a word driver circuit. The block selection circuit outputs a block selection signal based on an address signal. The redundancy main word decoder generates a redundancy main word signal in response to the block selection signal. The word reset circuit outputs a word reset signal in response to the redundancy main word signal. The word driver circuit drives one of word lines in response to the word reset signal, a main word signal indicating selection of the word driver circuit, and a word decode signal indicating selection of the one of word lines.

Abstract: In a semiconductor memory device including a data bus, a data bus charging circuit for charging the data bus, a data bus discharging circuit for discharging the data bus in accordance with a cell read data signal, and a push-pull type output circuit formed by a first N-channel MOS transistor connected between a first power supply terminal and an output terminal and a second N-channel MOS transistor connected between the output terminal and a second power supply terminal, a step-up circuit is connected between the data bus and a gate of the first N-channel MOS transistor to generate a step-up voltage in accordance with a voltage at the data bus.

Abstract: A semiconductor memory apparatus comprises a plurality of complementary bit line pairs for accessing memory cells. Each of the memory cells is accessed by two complementary bit line pairs. Each of the complementary bit line pairs is connected to a corresponding sense amp circuit for amplifying a signal level difference between bit lines of a corresponding bit line pair. A plurality of sealed lines, each being connected to ground and being positioned between two adjacent bit lines of different complementary bit line pairs, are provided to avoid the formation of a line-to-line capacitance between the two adjacent bit lines.