Abstract: A computer file management system allowing at least one of one file (F1) and/or one directory (D3) to belong to two or more directories (D1, D2). The file management system is characterized in that a file or directory specified by an operator of the computer or the program operating on the computer as an object to be operated has all the directories present on the directory path as parent directories. This system is a novel file management system capable of classifying/organizing files and directories more easily and naturally in the conventional system without requiring additional operation.

Abstract: A computer file management system allowing at least one of one file (F1) and/or one directory (D3) to belong to two or more directories (D1, D2). The file management system is characterized in that a file or directory specified by an operator of the computer or the program operating on the computer as an object to be operated has all the directories present on the directory path as parent directories. This system is a novel file management system capable of classifying/organizing files and directories more easily and naturally in the conventional system without requiring additional operation.

Abstract: A computer file management system allowing at least one of one file (F1) and/or one directory (D3) to belong to two or more directories (D1, D2). The file management system is characterized in that a file or directory specified by an operator of the computer or a program operating on the computer as an object to be operated has all the directories present on the directory path as parent directories. This system is a novel file management system capable of classifying/organizing files and directories more easily and naturally than in the conventional system without requiring additional operation.

Abstract: A versatile SDIO host controller capable of connecting to standardized general interfaces is provided. An SDIO host controller as a one-chip semiconductor integrated circuit device comprising: at least one core of an SDIO host, the core including an SD host engine and an SD host register set and memory that control the SD host engine; a plurality of CPU interfaces that control the SDIO host; and at least one selector that selects among the CPU interfaces. In particular, the SDIO host controller preferably comprises at least an ATA interface and an ATA-SD protocol conversion engine.

Abstract: The present invention provides an SDIO controller, an SDIO wireless communication card, an SDIO wireless communications module, and a method for transmitting write data from an SDIO host device to an SDIO application. Specifically, the SDIO controller is a single-chip semiconductor device connecting an SDIO-compliant SDIO host device with a plurality of applications via an SD bus, wherein the controller includes: (a) an SD interface operably connectable with the SDIO host device to decode commands received from the SDIO host device, and to return a response to the SDIO host device; (b) one or more application interfaces; and (c) a temporary memory operably connected between the SD interface and the one or more application interfaces.

Abstract: A versatile SDIO host controller capable of connecting to standardized general interfaces is provided. An SDIO host controller as a one-chip semiconductor integrated circuit device comprising: at least one core of an SDIO host, the core including an SD host engine and an SD host register set and memory that control the SD host engine; a plurality of CPU interfaces that control the SDIO host; and at least one selector that selects among the CPU interfaces. In particular, the SDIO host controller preferably comprises at least an ATA interface and an ATA-SD protocol conversion engine.

Abstract: A versatile SDIO host controller capable of connecting to standardized general interfaces is provided. An SDIO host controller as a one-chip semiconductor integrated circuit device comprising: at least one core of an SDIO host, the core including an SD host engine and an SD host register set and memory that control the SD host engine; a plurality of CPU interfaces that control the SDIO host; and at least one selector that selects among the CPU interfaces. In particular, the SDIO host controller preferably comprises at least an ATA interface and an ATA-SD protocol conversion engine.

Abstract: The present invention provides an SDIO controller, an SDIO wireless communication card, an SDIO wireless communications module, and a method for transmitting write data from an SDIO host device to an SDIO application. Specifically, the SDIO controller is a single-chip semiconductor device connecting an SDIO-compliant SDIO host device with a plurality of applications via an SD bus, wherein the controller includes: (a) an SD interface operably connectable with the SDIO host device to decode commands received from the SDIO host device, and to return a response to the SDIO host device; (b) one or more application interfaces; and (c) a temporary memory operably connected between the SD interface and the one or more application interfaces.

Abstract: The present invention provides an SDIO controller, an SDIO wireless communication card, an SDIO wireless communications module, and a method for transmitting write data from an SDIO host device to an SDIO application. Specifically, the SDIO controller is a single-chip semiconductor device connecting an SDIO-compliant SDIO host device with a plurality of applications via an SD bus, wherein the controller includes: (a) an SD interface operably connectable with the SDIO host device to decode commands received from the SDIO host device, and to return a response to the SDIO host device; (b) one or more application interfaces; and (c) a temporary memory operably connected between the SD interface and the one or more application interfaces.

Abstract: A computer file management system allowing at least one of one file (F1) and/or one directory (D3) to belong to two or more directories (D1, D2). The file management system is characterized in that a file or directory specified by an operator of the computer or a program operating on the computer as an object to be operated has all the directories present on the directory path as parent directories. This system is a novel file management system capable of classifying/organizing files and directories more easily and naturally than in the conventional system without requiring additional operation.

Abstract: The present invention provides an SDIO controller, an SDIO wireless communication card, an SDIO wireless communications module, and a method for transmitting write data from an SDIO host device to an SDIO application. Specifically, the SDIO controller is a single-chip semiconductor device connecting an SDIO-compliant SDIO host device with a plurality of applications via an SD bus, wherein the controller includes: (a) an SD interface operably connectable with the SDIO host device to decode commands received from the SDIO host device, and to return a response to the SDIO host device; (b) one or more application interfaces; and (c) a temporary memory operably connected between the SD interface and the one or more application interfaces.

Abstract: A FIFO memory having multiple buffer areas formed therein, and boundary pointers for defining the size of each buffer area. The FIFO memory also includes a controller operable for dynamically varying the value of each boundary pointer in accordance with the amount of incoming data to be stored in a given buffer area during the operation of the device so as to allow for maximum utilization of the memory space.

Abstract: In a processor employing a delayed branch method, delayed branch control which does not complicate instruction execution sequence and improves the readability of a program on the assembler level is implemented without providing a control bit in an instruction code. The delayed branch control according to the present invention involves the use of a branch-information storing circuit for storing the occurrence or nonoccurrence of a branch in a specified one of a continuous sequence of cycles immediately before a current execute cycle which are equal in number to delay slots in the processor. In executing a delayed branch instruction, when the branch-information storing circuit stores the occurrence of a branch in the specified cycle, a branch is disabled. This prevents instruction execution sequence from being complicated even when individual branch conditions for consecutive delayed branch instructions are satisfied, so that the program on the assembler level is improved in readability.

Abstract: In a processor employing a delayed branch method, delayed branch control which does not complicate instruction execution sequence and improves the readability of a program on the assembler level is implemented without providing a control bit in an instruction code. The delayed branch control according to the present invention involves the use of a branch-information storing circuit for storing the occurrence or nonoccurrence of a branch in a specified one of a continuous sequence of cycles immediately before a current execute cycle which are equal in number to delay slots in the processor. In executing a delayed branch instruction, when the branch-information storing circuit stores the occurrence of a branch in the specified cycle, a branch is disabled. This prevents instruction execution sequence from being complicated even when individual branch conditions for consecutive delayed branch instructions are satisfied, so that the program on the assembler level is improved in readability.

Abstract: This invention provides a code generator for reduction of the power consumption of digital signal processors. A plurality of codes are prepared for an item of data. A code with the lowest polarity-inverting bit count for input data, is selected from among the prepared codes. The code generator of the present invention has a code generation section, a code selection section and a code output section. The code generation section inputs data from a data file and generates all codes allocated to the input data. The code selection section makes a comparison between each of the generated codes and a code that is transferred just before or after any one of the generated codes is transferred over a bus of the digital signal processor, in order to select from among the generated codes a code having the lowest polarity-inverting bit count. The code output section writes the selected code into a code file.