Abstract: According to one embodiment, an information processor comprises an error detection circuit having at least one of a synchronous byte interval detection circuit, a synchronous byte comparison circuit and an error indication comparison circuit which receives digital information, transmitted as packet data, by a digital tuner unit and detects packet data having defects as an error in the sequentially received packet data from intervals of synchronous bytes, values of the synchronous bytes or values of error indications, and mounts a digital broadcast receiver to reproduce information from the packet data from which the packet data having the defects have been removed.

Abstract: According to one embodiment, an information processing apparatus includes an internal receiving unit which is connected to an antenna terminal, a communicating unit which executes communication with an external receiver, a first determining unit which determines whether or not an antenna is connected to the antenna terminal, a second determining unit which determines whether or not communication between the external receiver and the communicating unit is executable, a detector which detects a route capable of receiving a broadcast data from a determination results of the first and second determining unit, a selection unit which selects one of the internal receiver and the external receiver corresponding to a detection result of the detecting unit, a reproduction unit which reproduces broadcast data, and an interrupting unit which, unless the detecting unit detects a route capable of receiving the broadcast data, interrupts supply of power to the internal receiver and the communicating unit.