Abstract: An inference apparatus provides target data to multiple inference models to cause the inference models each derived from local learning data obtained in a different environment to perform predetermined inference to obtain an inference result from each of the inference models. The inference apparatus determines the value of each combining parameter using environment data, weights the inference result from each of the inference models using the determined value of each combining parameter, and combines the weighted inference result from each inference model together to generate an inference result in a target environment.

Abstract: Provided is a magnetic sensor device including: a current input terminal; a voltage input terminal; an output terminal; a magnetic sensor circuit including a first terminal, one of one Hall element and a set of Hall elements connected in parallel to each other, and a pilot signal generating circuit; a chopper modulator/demodulator circuit including a first mixer connected to the magnetic sensor circuit, an amplifier containing an input port connected to the first mixer, a second mixer containing an input port connected to the amplifier, and an output port connected to the output terminal; and a feedback circuit including a second terminal connected to the chopper modulator/demodulator circuit, a third mixer, a voltage-current conversion circuit, and a third terminal connected to the current input terminal and the first terminal, and a fourth terminal connected to the voltage input terminal.

Abstract: Provided is a magnetic sensor device including: a current input terminal; a voltage input terminal; an output terminal; a magnetic sensor circuit including a first terminal, one of one Hall element and a set of Hall elements connected in parallel to each other, and a pilot signal generating circuit; a chopper modulator/demodulator circuit including a first mixer connected to the magnetic sensor circuit, an amplifier containing an input port connected to the first mixer, a second mixer containing an input port connected to the amplifier, and an output port connected to the output terminal; and a feedback circuit including a second terminal connected to the chopper modulator/demodulator circuit, a third mixer, a voltage-current conversion circuit, and a third terminal connected to the current input terminal and the first terminal, and a fourth terminal connected to the voltage input terminal.

Abstract: Provided is a relaxation oscillator having an extremely small temperature deviation in oscillation frequency. A first current (I1) generated by a reference voltage source and a first resistor having a positive first-order temperature coefficient is supplied to a first variable capacitor (C1) for oscillation, and a second current (I2) generated by a reference voltage source and a second resistor having a negative first-order temperature coefficient is supplied to a second variable capacitor (C2) for oscillation. A product of a value of a ratio of a first current to a second current and a value of a ratio of a first-order temperature coefficient of the second resistor to a first-order temperature coefficient of the first resistor, and a value of a ratio of a capacitance of the first variable capacitor to a capacitance of the second variable capacitor have the same absolute value and opposite signs.

Abstract: Provided is a relaxation oscillator having an extremely small temperature deviation in oscillation frequency. A first current (I1) generated by a reference voltage source and a first resistor having a positive first-order temperature coefficient is supplied to a first variable capacitor (C1) for oscillation, and a second current (I2) generated by a reference voltage source and a second resistor having a negative first-order temperature coefficient is supplied to a second variable capacitor (C2) for oscillation. A product of a value of a ratio of a first current to a second current and a value of a ratio of a first-order temperature coefficient of the second resistor to a first-order temperature coefficient of the first resistor, and a value of a ratio of a capacitance of the first variable capacitor to a capacitance of the second variable capacitor have the same absolute value and opposite signs.

Abstract: There is provided a digital radio transmitter capable of meeting a legal standard even if unwanted emissions resulting from a switching frequency of a switching power supply occur in transmission waves. The digital radio transmitter includes: a switching power supply that determines a switching frequency by a synchronization signal of an oscillator; a data readout/transfer circuit that determines a transfer timing frequency of baseband data based on the synchronization signal of the oscillator; and a power amplifier using, as a VCC power source, voltage output from the switching power supply.

Abstract: A sync clock signal for information reproduction is generated using a binary signal obtained from a recording medium as a reference signal. The phase of the binary signal is compared with that of the sync clock signal. A frequency is changed based on the comparison result to generate (2m+1) multi-phase clock signals mutually shifted in phase by an integral multiple of 2&pgr;/(2m+1). Any one of these clock signals is used as the sync clock signal for information reproduction. The binary signal is delayed by a controllable delay time to generate a binary delayed signal, the phase of which is compared with those of the clock signals. The delay time of the binary delayed signal is controlled based on the comparison result so that the level change timing of the binary delayed signal is moved on a time base away from that of the sync clock signal.

Abstract: A sync clock signal for information reproduction is generated using a binary signal obtained from a recording medium as a reference signal. The phase of the binary signal is compared with that of the sync clock signal. A frequency is changed based on the comparison result to generate (2m+1) multi-phase clock signals mutually shifted in phase by an integral multiple of 2&pgr;/(2m+1). Any one of these clock signals is used as the sync clock signal for information reproduction. The binary signal is delayed by a controllable delay time to generate a binary delayed signal, the phase of which is compared with those of the clock signals. The delay time of the binary delayed signal is controlled based on the comparison result so that the level change timing of the binary delayed signal is moved on a time base away from that of the sync clock signal.