Patents by Inventor Hirozi Yamada
Hirozi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6889431Abstract: The present invention provides a manufacturing method of an electronic circuit device including a multi-layer circuit board incorporated with a thin film capacitor small in size and of high performance capable of attaining higher capacitance value with a thin dielectric film of high dielectric constant and with favorable film quality. A first electrode layer and a thin film dielectric layer are laminated continuously in this order in one identical to laminate each of the layers on a leveled substrate in one identical chamber and then the first electrode layer is fabricated a conductor pattern.Type: GrantFiled: February 21, 2002Date of Patent: May 10, 2005Assignees: Hitachi, Ltd., Hitachi Chemical Co., Ltd.Inventors: Hiroshi Okabe, Hirozi Yamada, Eriko Takeda, Kazunori Yamamoto, Hiroyuki Kuriya, Masanori Yamaguchi, Kazuhisa Otsuka, Yoshitaka Hirata, Yasushi Shimada
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Patent number: 6757178Abstract: In an electronic circuit equipment using a multilayer circuit board on which a semiconductor chip is mounted, a thin film capacitor is provided on the multilayer circuit board. Moreover, a first electrode of the thin film capacitor and a first wiring of the multilayer circuit board are electrically connected to each other, and a second electrode of the thin film capacitor and a second wiring of the multilayer circuit board are electrically connected to each other, respectively. Furthermore, a thin film dielectric of the thin film capacitor was grown epitaxially with the first electrode as its base. The employment of the multilayer circuit board makes it possible to provide the electronic circuit equipment using the multilayer circuit board that includes the built-in thin film capacitor having the high dielectric-constant thin film dielectric.Type: GrantFiled: January 15, 2002Date of Patent: June 29, 2004Assignee: Renesas Technology Corp.Inventors: Hiroshi Okabe, Hirozi Yamada
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Publication number: 20030097750Abstract: The present invention provides a manufacturing method of an electronic circuit device including a multi-layer circuit board incorporated with a thin film capacitor small in size and of high performance capable of attaining higher capacitance value with a thin dielectric film of high dielectric constant and with favorable film quality. A first electrode layer and a thin film dielectric layer are laminated continuously in this order in one identical to laminate each of the layers on a leveled substrate in one identical chamber and then the first electrode layer is fabricated a conductor pattern.Type: ApplicationFiled: February 21, 2002Publication date: May 29, 2003Applicant: Hitachi, Ltd.Inventors: Hiroshi Okabe, Hirozi Yamada, Eriko Takeda, Kazunori Yamamoto, Hiroyuki Kuriya, Masanori Yamaguchi, Kazuhisa Otsuka, Yoshitaka Hirata, Yasushi Shimada
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Publication number: 20020118523Abstract: In an electronic circuit equipment using a multilayer circuit board on which a semiconductor chip is mounted, a thin film capacitor is provided on the multilayer circuit board. Moreover, a first electrode of the thin film capacitor and a first wiring of the multilayer circuit board are electrically connected to each other, and a second electrode of the thin film capacitor and a second wiring of the multilayer circuit board are electrically connected to each other, respectively. Furthermore, a thin film dielectric of the thin film capacitor was grown epitaxially with the first electrode as its base. The employment of the multilayer circuit board makes it possible to provide the electronic circuit equipment using the multilayer circuit board that includes the built-in thin film capacitor having the high dielectric-constant thin film dielectric.Type: ApplicationFiled: January 15, 2002Publication date: August 29, 2002Applicant: Hitachi, Ltd.Inventors: Hiroshi Okabe, Hirozi Yamada
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Patent number: 5124583Abstract: A DC powered integrated circuit includes a plurality of magnetic flux coupling type Josephson elements. First and second Josephson elements are connected in series to form a first element series circuit of Josephson elements. Third and fourth Josephson elements are connected in series to form a second element series circuit of Josephson elements. The first and second element series circuits are connected in series to form a huffle circuit, with a load inductance, three resistors and a DC current source.Type: GrantFiled: February 5, 1991Date of Patent: June 23, 1992Assignee: Hitachi, Ltd.Inventors: Yuji Hatano, Shinichiro Yano, Hiroyuki Mori, Hirozi Yamada, Mikio Hirano
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Patent number: 4904619Abstract: A method of producing a Josephson junction device consisting of thin films of superconducting materials such as niobium and niobium nitride that work at cryogenic temperatures, in which a base electrode layer, tunnel barrier layer and a counterelectrode layer constituting a Josephson junction are formed on a substrate. In order to form a desired electrode pattern on the counterelectrode layer, a resist pattern is used as a mask for dry etching, followed by a plasma ashing process for ablating part of the resist in order to form a terrace-shaped portion at the edges and corners of the counterelectrode pattern by reforming and shrinking the cross-sectional geometry of the resist. Then, a thin insulating film for covering the edged layers is deposited over the entire surface of substrate, followed by the removal of said resist pattern together with said insulating film deposited on said resist pattern in order to form a protecting layer around the counterelectrode pattern.Type: GrantFiled: February 1, 1988Date of Patent: February 27, 1990Assignee: Hitachi Ltd.Inventors: Hirozi Yamada, Sachiko Kizaki, Hiroyuki Mori, Yoshinobu Tarutani, Mikio Hirano
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Patent number: 4344153Abstract: A magnetic bubble memory device and a method of fabricating the device are disclosed in which a conductor pattern lies at least between a film for maintaining magnetic bubbles therein, and a soft magnetic material pattern. Further, the magnetic bubble memory device can be formed precisely without suffering from errors due to mask alignment, by employing a mask provided with a plurality of patterns which are different in transmittance.Type: GrantFiled: April 13, 1979Date of Patent: August 10, 1982Assignee: Hitachi, Ltd.Inventors: Hideki Nishida, Hirozi Yamada, Hiroshi Umezaki, Yutaka Sugita, Norikazu Tsumita
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Patent number: 4319256Abstract: A sandwich-type Josephson junction element wherein a counter electrode is made of a Mo-Re alloy which contains 10-90 atomic-% of Re. The Josephson junction element has a high operating temperature, and any deterioration thereof attributed to a thermal cycle is not noted.Type: GrantFiled: May 2, 1980Date of Patent: March 9, 1982Assignee: Hitachi, Ltd.Inventors: Yoshinobu Tarutani, Hirozi Yamada, Ushio Kawabe
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Patent number: 4288283Abstract: A method of forming a microscopic pattern wherein the object to be etched is overlaid with a film made of a material which is highly immune to etching and further provided with a reflection reducing film. Thus, the reflection of the irradiating ultraviolet rays by the underlying layer is effectively prevented.Type: GrantFiled: January 8, 1980Date of Patent: September 8, 1981Assignee: Hitachi, Ltd.Inventors: Hiroshi Umezaki, Hideki Nishida, Norikazu Tsumita, Hirozi Yamada, Katsuhiro Kaneko, Nagatugu Koiso
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Patent number: 4262054Abstract: A magnetic bubble memory device is disclosed in which a hardened film made of a heat-resisting highly-polymerized organic resin and having a predetermined thickness is employed for an insulating film interposed between a conductor pattern and a soft magnetic material pattern. In a conventional magnetic bubble memory device in which the above-mentioned insulating film is made of SiO.sub.2, an abrupt step is produced in the soft magnetic material pattern due to the existence of the conductor pattern beneath a portion of the soft magnetic material pattern, and the margin of bias magnetic field is thereby lowered. According to the present invention, the step is reduced and smoothed, and thus the lowering of the margin can be prevented.Type: GrantFiled: August 3, 1979Date of Patent: April 14, 1981Assignee: Hitachi, Ltd.Inventors: Hiroshi Umezaki, Hideki Nishida, Hirozi Yamada, Yutaka Sugita, Katsuhiro Kaneko, Nagatugu Koiso, Masatake Takahashi, deceased
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Patent number: 3977243Abstract: A testing machine for a tire on an imitation road in which a tire to be tested is urged against a crawler with the aid of a cantilever arm connected through a crosshead to a lifting and lowering disc engaged with screw threaded rods rotatably mounted in a machine frame. The crawler is composed of an endless chain and a road surface forming rods detachably mounted on the endless chain and replaceable by new rods made of different kind of material. In the crosshead are incorporated slip and camber angle setting mechanisms. Provision is made of load cells such as a strain gauge operatively connected to a tire supporting shaft, driving and driven shafts of the crawler and a guide rail of the crawler and for detecting a vertical load subjected to the tire, a torque for driving the crawler under various load conditions and a transverse component of force subjected to the crawler when the tire having a given slip angle or a camber angle is urged against the crawler.Type: GrantFiled: July 29, 1975Date of Patent: August 31, 1976Assignee: Bridgestone Tire Company LimitedInventors: Hirozi Yamada, Hiroshi Ogawa, Satoru Aono, Hironori Hirano