Abstract: A distance measuring device has a plurality of light receiving elements each of which receives a reflected optical signal reflected by an object, and an image processor that generates a distance image in accordance with distances to the object, based on signal intensities and light reception timings of the reflected optical signal received by the plurality of light receiving elements, wherein the image processor detects a direction of the object, based on at least either the signal intensities of the reflected optical signal received by the light receiving elements or the distances to the object measured based on the reflected optical signal, and divides at least one or some of pixels included in the distance image, based on the direction of the detected object.

Abstract: An image processing apparatus has a light source that emits a light signal at a predetermined time interval, a scanner capable of changing at least one of a scanning range or a scanning timing of the light signal for each of frames, a light receiver that receives a reflected light signal reflected on an object by irradiating the object with the light signal, processing circuitry that generates a distance image for each of the frames based on the reflected light signal received by the light receiver, and synthesizes the distance images of a plurality of the frames to generate a high-resolution distance image.

Abstract: A distance measuring device according to the present embodiment comprises an averaging processor, a detector, and a distance measuring circuit. The averaging processor is configured to average a digital signal obtained by digitizing reflected light of laser light and generate a time-series luminance signal. The detector is configured to detect a rise time at which the time-series luminance signal reaches a threshold. The distance measuring circuit is configured to measure a distance to an object based on a time difference between the rise time and a radiation timing of the laser light.

Abstract: According to one embodiment, a decoding device decodes a (k+m) bit codeword in accordance with a check matrix. The codeword includes k-bit information symbols and an m-bit parity check code. The check matrix includes a unit matrix and a coefficient matrix. The most significant bit of each of a second vector to a last vector in the coefficient matrix is 1. Binary codes with values 1 to k?1 are sequentially arranged from the second vector to the last vector in a matrix which is obtained by excluding the most significant bits of the second to the last vectors from the matrix including the second to the last vectors. A first vector of the coefficient matrix disagrees with the other vectors in the check matrix, and the first vector is composed of a specified bit pattern having a most significant bit of 0.

Abstract: A propagation path specifying device includes: a storing unit storing first information correspondingly indicating signal changes occurring in the input terminals and output terminals of the plurality of logic elements and occurring times of the signal changes; a storing unit storing second information indicating a connection relation among a plurality of logic elements having one or more input terminals and output terminals; a storing unit storing third information indicating a correspondence of signals in the input terminal and output terminal of the logic element; an input unit inputting information to select the output terminal of the plurality of logic elements and the occurring time from the first information; and a propagation path specifying unit retroactively specifying a propagation path of the signal change in the selected output terminal and at the selected occurring time, based on the first to third information.

Abstract: According to one embodiment, a decoding device decodes a (k+m) bit codeword in accordance with a check matrix. The codeword includes k-bit information symbols and an m-bit parity check code. The check matrix includes a unit matrix and a coefficient matrix. The most significant bit of each of a second vector to a last vector in the coefficient matrix is 1. Binary codes with values 1 to k?1 are sequentially arranged from the second vector to the last vector in a matrix which is obtained by excluding the most significant bits of the second to the last vectors from the matrix including the second to the last vectors. A first vector of the coefficient matrix disagrees with the other vectors in the check matrix, and the first vector is composed of a specified bit pattern having a most significant bit of 0.