Patents by Inventor Hisaaki Tominaga
Hisaaki Tominaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050179106Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: April 12, 2005Publication date: August 18, 2005Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20050167785Abstract: In a bipolar transistor, an SIC layer is provided right under a genuine base region in order to suppress the Kirk effect and improve fT characteristic by thinning the film of the genuine base region. The higher the concentration of impurities in the SIC layer, the bigger the effect. When the impurity concentration of the SIC layer is high, the VCEO deteriorates so that the fT characteristic improvement and the Kirk effect suppression are in a trade off relationship with the VCEO. A second SIC layer is provided right under the genuine base region and in contact therewith, and a first SIC layer with a higher impurity concentration than the second SIC layer is formed right under the second SIC layer. The first SIC layer narrows the collector width and suppresses the Kirk effect whereas, the second SIC layer makes it possible to improve fT characteristic by cutting a lower edge of the genuine base region.Type: ApplicationFiled: December 29, 2004Publication date: August 4, 2005Applicant: Sanyo Electric Co., Ltd.Inventors: Hisaaki Tominaga, Keita Odajima, Shigehito Matsumoto, Masamichi Yamamuro
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Patent number: 6818492Abstract: This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance is further reduced, and the base-emitter capacitance is also reduced. A base electrode layer makes a contact with the whole surface of the base region. A tapered trench is provided in the base region. A finer emitter region is formed by emitter diffusion from the bottom portion of the trench. Since the base electrode is formed adjacently to the trench, the distance between an active region of the base and the base electrode layer can be shortened and a larger grounded area of a base can also be obtained, therefore the base resistance can be substantially reduced. In addition, by forming a fine region, the base-emitter capacitance between the base and emitter can also be reduced, therefore a transistor excellent in high-frequency characteristics can be obtained.Type: GrantFiled: December 17, 2001Date of Patent: November 16, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Hirotoshi Kubo, Shigeyuki Murai, Hisaaki Tominaga, Hidetaka Sawame
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Patent number: 6787871Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.Type: GrantFiled: October 30, 2002Date of Patent: September 7, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6777277Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: GrantFiled: July 26, 2002Date of Patent: August 17, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6682968Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: GrantFiled: July 26, 2002Date of Patent: January 27, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6627967Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: GrantFiled: July 26, 2002Date of Patent: September 30, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 6617660Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof. The field effect transistor semiconductor of this invention comprises a source/drain electrode 6 positioned in a predetermined position in a GaAs substrate 1, a channel region provided in the GaAs substrate 1 and between the source/drain electrodes 6, a gate electrode 11 which is in schottky contact with a part of a channel region and is positioned between the source/drain electrodes 6, and an insulating film 7 which electrically insulates a surface of the GaAs substrate and the gate electrode 11 at both side surfaces of the gate electrode 11.Type: GrantFiled: September 8, 1999Date of Patent: September 9, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Shigeyuki Murai, Emi Fujii, Shigeharu Matsushita, Hisaaki Tominaga
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Publication number: 20030113985Abstract: This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof.Type: ApplicationFiled: September 8, 1999Publication date: June 19, 2003Inventors: SHIGEYUKI MURAI, EMI FUJII, SHIGEHARU MATSUSHITA, HISAAKI TOMINAGA
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Publication number: 20030094668Abstract: An integrated Schottky barrier diode chip includes a compound semiconductor substrate, a plurality of Schottky barrier diodes formed on the substrate and an insulating region formed on the substrate by an on implantation. The insulating region electrically separates a portion of a diode at a cathode voltage from a portion of the diode at an anode voltage. Because of the absence of a polyimide layer and trench structures, this planar device configuration results in simpler manufacturing method and improved device characteristics.Type: ApplicationFiled: October 30, 2002Publication date: May 22, 2003Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030089959Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: May 15, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030060031Abstract: A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: March 27, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onada, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030036252Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: February 20, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030025175Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: February 6, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20020127814Abstract: This invention provides a semiconductor device which is excellent in high-frequency characteristics, wherein emitter diffusion is performed by a trench formed in a base region, the base resistance is further reduced, and the base-emitter capacitance is also reduced. A base electrode layer makes a contact with the whole surface of the base region. A tapered trench is provided in the base region. A finer emitter region is formed by emitter diffusion from the bottom portion of the trench. Since the base electrode is formed adjacently to the trench, the distance between an active region of the base and the base electrode layer can be shortened and a larger grounded area of a base can also be obtained, therefore the base resistance can be substantially reduced. In addition, by forming a fine region, the base-emitter capacitance between the base and emitter can also be reduced, therefore a transistor excellent in high-frequency characteristics can be obtained.Type: ApplicationFiled: December 17, 2001Publication date: September 12, 2002Inventors: Hirotoshi Kubo, Shigeyuki Murai, Hisaaki Tominaga, Hidetaka Sawame