Patents by Inventor Hisae Yamamura

Hisae Yamamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6622054
    Abstract: With a view to providing a monitoring system for the quality and manufacturing conditions of electronic circuits capable of facilitating the grasping of correlation's between diverse manufacturing conditions and manufacturing states, statistically characteristic images are selected out of a group of images retrieved from a detection information database by specifying at least one out of the values of feature quantities, design information and manufacturing conditions, and are displayed.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: September 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hirohito Okuda, Toshifumi Honda, Hisae Yamamura, Yuji Takagi, Hideaki Doi, Shigeshi Yoshinaga
  • Patent number: 6333992
    Abstract: A defect judgement processing method and apparatus which can optimize image processing and defect judgement parameters for a detection image cut out by each inspection window to avoid erroneous judgement and defect missing and to realize reliable defect judgement.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: December 25, 2001
    Assignees: Hitachi, Ltd., Siemens Aktiengesellschaft
    Inventors: Hisae Yamamura, Yukio Matsuyama, Toshifumi Honda, Ludwig Listl
  • Patent number: 5780866
    Abstract: A method for automatic focusing and three dimensional profile detection and an apparatus for automatic focusing and three dimensional profile detection have the purpose of detecting a three dimensional profile of the state of mounting of parts or soldering on a board without the affects of warp, even if the board of the detection object is warped, as if the surface of the board were on a flat plane. The board surface height is detected in a plurality of windows corresponding to stage scanning regions from a three dimensional profile signal of the part-mounted board detected by a height detection optical system. The board height or inclination in the next window is forecasted from the board surface height and the control history of stage height in the already-detected plurality of windows.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: July 14, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hisae Yamamura, Yukio Matsuyama, Takanori Ninomiya, Hideaki Sasazawa
  • Patent number: 5459794
    Abstract: A measuring method and apparatus for automatically and accurately measuring the sizes of portions of a hybrid integrated circuit chip and circuit patterns formed thereon or a wiring board and wiring patterns formed thereon. An image of a portion of a hybrid integrated circuit chip or wiring board is obtained through a TV camera which provides image signals representing images including those of objective portions. The image signals are processed to calculate the positions of the objective portions automatically. The size of an arbitrary objective portion is determined from a difference between respective positions of other objective portions.
    Type: Grant
    Filed: July 15, 1993
    Date of Patent: October 17, 1995
    Inventors: Takanori Ninomiya, Hisae Yamamura
  • Patent number: 5373471
    Abstract: In case an address is to access a defective memory cell, a defective memory cell in a memory cell area contained in one of paired memory mats is selected in parallel with a redundant memory cell in a redundant memory cell area contained in the other memory mat. At this time of selecting the redundant main word line for selecting the redundant memory cell, there is not required the logical operation for deciding whether or not the redundant use of the access address fed from the outside is proper. For example, the redundant main word line is set to the select level on the basis of a chip select signal. As a result, the drive start timing of the redundant main word line is not delayed in the least from the drive start timing of the main word line. Thus, it is possible to prevent the event that the select drive timing of the redundant sub word line is delayed on account of the delay in the drive timing of the redundant main word line.
    Type: Grant
    Filed: August 25, 1992
    Date of Patent: December 13, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Saeki, Kiyoshi Nagai, Hisae Yamamura, Tadashi Abe, Takeshi Fukazawa