Patents by Inventor Hisafumi Iwata

Hisafumi Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020143483
    Abstract: In the wafer production process of a semiconductor integrated circuit, an inspection system and an inspection apparatus that convert and output a yield loss at high accuracy from the result of a defect inspection, such as a dark-field inspection and a bright-field inspection without waiting for the result of the final probing test. Defect map data read processing and kill ratio computation data read processing are performed. Subsequently, kill ratio computation processing every defect computes a kill ratio every defect using defect map data and kill ratio computation data. Subsequently, kill ratio computation processing every chip computes a kill ratio every LSI chip using the kill ratio every defect. Subsequently, yield loss computation processing computes a yield loss of the defect map data using the kill ratio every chip and yield loss output processing outputs the computation result.
    Type: Application
    Filed: February 22, 2002
    Publication date: October 3, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Makoto Ono, Hisafumi Iwata
  • Publication number: 20020052053
    Abstract: A method and system are provided for analyzation of those defects with possibility to become electrical failures with higher priority during inspection processes of particles and/or pattern defects of a wafer for formation of electronic devices such as semiconductor integrated circuits.
    Type: Application
    Filed: October 30, 2001
    Publication date: May 2, 2002
    Inventors: Makoto Ono, Hisafumi Iwata, Keiko Kirino
  • Patent number: 5684565
    Abstract: A method and apparatus is disclosed for detecting a pattern image of each of a plurality of patterns on the surface of an object. Light emitted from either a light source including a wide wavelength or a light source including a plurality of monowavelengths is applied to the object. The object includes a layered structure having a plurality of layers, wherein at least a part of an uppermost layer of the object is optically transparent. Spectral illumination intensity characteristics of the light emitted from the light source is varied, depending on information about both the layered structure of the object, and a material of the object to obtain a desired spectral illumination intensity, and a pattern image of each of patterns is detected as either a one-dimensional or a two-dimensional image based on light reflected from the object.
    Type: Grant
    Filed: September 12, 1994
    Date of Patent: November 4, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitada Oshida, Hisafumi Iwata, Yasuhiro Yoshitake, Minoru Yoshida, Yukihiro Shibata
  • Patent number: 5293538
    Abstract: A defect inspection method and apparatus detect a defect which exists on the surface of a protection layer or a defect which exists in the protection layer and scatters the light on its surface, through the detection of the light which is derived from an illumination light and reflected on the protection layer surface and the light which is derived from a slit-formed illumination light and scattered in the area between the position where the light is incident to the transparent protection layer and the position where the surface of an element underneath the transparent protection layer is illuminated.
    Type: Grant
    Filed: May 24, 1991
    Date of Patent: March 8, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Hisafumi Iwata, Yukio Matsuyama, Hitoshi Kubota
  • Patent number: 5278012
    Abstract: A method for producing a thin film multilayer substrate having a base substrate, and, which a plurality of conductor pattern layers superposed thereon through dielectric layers therebetween comprises the steps of: optically detecting the uppermost conductor pattern layer whenever the conductor pattern layer is formed on the base substrate; inspecting an absence and/or presence of a fault of the conductor pattern layer; and repairing a faulty portion in accordance with fault position data detected by the inspecting. According to this method, it is possible to enhance a production yield of relatively large size of thin film multilayer substrates which needs a relatively small amount of production at a high production cost, for mounting LSI chips thereon.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: January 11, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Chie Yamanaka, Toshiaki Ichinose, Takanori Ninomiya, Hisafumi Iwata, Yasuo Nakagawa, Nobuyuki Akiyama
  • Patent number: 5059559
    Abstract: The present invention relates to a multi-pin chip mounting method and apparatus based on a TAB (Tape Automated Bonding) system in which leads formed on a tape and bumps formed an IC chip are aligned with each other and compress-bonded to each other. An IC chip having bumps formed on a surface thereof and inner leads formed on a carrier tape are disposed opposite to each other at a bonding station. A position of the IC chip on a stage is detected through the inner leads at the bonding station to determine the amount of correction of position of the stage. The inner leads and the IC chip are aligned with each other on the basis of the determined correction amount and are thereafter bonded to each other.
    Type: Grant
    Filed: November 1, 1988
    Date of Patent: October 22, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Michio Takahashi, Tooru Mita, Yasuo Nakagawa, Toshimitsu Hamada, Hisafumi Iwata, Aizo Kaneda, Kouji Serizawa, Hiroyuki Tanaka, Koichi Sugimoto, Toshihiko Sakai, Keizo Matsukawa, Tsutomu Mimata