Patents by Inventor Hisaho Inao

Hisaho Inao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100320614
    Abstract: A semiconductor package production method includes the step of die-cutting part of a lead side portion of a seal formed by molding and dam bars using a pedestal and punch. The pedestal has an outer surface at a position retreating from a side surface of an upper seal portion as far as possible and an inner surface generally near a side surface of a lower seal portion. Width Wa of the upper surface of the pedestal is smaller than the overhang size of the upper seal portion. Tip region Ra of the lead side portion which is present right under the overhang portion of the upper seal portion has a slanted surface Fa1 which is sloped inwardly from top to bottom.
    Type: Application
    Filed: August 26, 2010
    Publication date: December 23, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Hisaho Inao, Tatsuya Hirano, Katsutoshi Shimizu
  • Patent number: 7808096
    Abstract: A semiconductor package production method includes the step of die-cutting part of a lead side portion of a seal formed by molding and dam bars using a pedestal and punch. The pedestal has an outer surface at a position retreating from a side surface of an upper seal portion as far as possible and an inner surface generally near a side surface of a lower seal portion. Width Wa of the upper surface of the upper surface of the pedestal is smaller than the overhang size of the upper seal portion. Tip end region Ra of the lead side portion which is present right under the overhang portion of the upper seal portion has a slanted surface Fa1which is sloped inwardly from top to bottom.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventors: Hisaho Inao, Tatsuya Hirano, Katsutoshi Shimizu
  • Publication number: 20080293190
    Abstract: A semiconductor device includes a semiconductor chip, leads for sending and receiving signals between the semiconductor chip and an external device, fine metal wires, an encapsulant for sealing the leads, and a lid member. On the surface of each of the leads, a metal oxide film is formed by an oxidation treatment. The metal oxide film has a thickness larger than a natural oxide film and no more than 80 nm.
    Type: Application
    Filed: June 24, 2008
    Publication date: November 27, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hisaho Inao, Tetsuya Hirano, Katsutoshi Shimizu
  • Patent number: 7402898
    Abstract: A semiconductor device includes a semiconductor chip, leads for sending and receiving signals between the semiconductor chip and an external device, fine metal wires, an encapsulant for sealing the leads, and a lid member. On the surface of each of the leads, a metal oxide film is formed by an oxidation treatment. The metal oxide film has a thickness larger than a natural oxide film and no more than 80 nm.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: July 22, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisaho Inao, Tatsuya Hirano, Katsutoshi Shimizu
  • Publication number: 20080132002
    Abstract: A method of producing semiconductor packages includes the step of punching out a dam-bar and part of the region lateral to a lead of a scaling body formed by molding, the punching-out being effected by using a support block and a punch. The support block has an outer lateral surface in a region receding as much as possible from the lateral surface of the upper portion of the seal body and also has an inner lateral surface almost flush with the lateral surface of the lower portion of the seal body. The width (Wa) of the upper surface of the support block is smaller than the overhang quantity of the upper portion of the seal body. In the region lateral to the lead, the front end region (Ra) positioned immediately below the overhang section of the upper portion of the seal body has an inclined surface (Fa1) sloping inwardly downward.
    Type: Application
    Filed: May 12, 2005
    Publication date: June 5, 2008
    Inventors: Hisaho Inao, Tatsuya Hirano, Katsutoshi Shimizu
  • Publication number: 20060027903
    Abstract: A semiconductor device includes a semiconductor chip, leads for sending and receiving signals between the semiconductor chip and an external device, fine metal wires, an encapsulant for sealing the leads, and a lid member. On the surface of each of the leads, a metal oxide film is formed by an oxidation treatment. The metal oxide film has a thickness larger than a natural oxide film and no more than 80 nm.
    Type: Application
    Filed: August 4, 2005
    Publication date: February 9, 2006
    Inventors: Hisaho Inao, Tatsuya Hirano, Katsutoshi Shimizu
  • Patent number: 6645792
    Abstract: The lead frame of the present invention is a lead frame used in resin encapsulation of a semiconductor chip using an encapsulation mold that includes a die cavity to be filled with an encapsulation resin, the lead frame including: a first region exposed to the die cavity; a second region that is surrounding the first region and to be clamped by the encapsulation mold; a third region exposed to an ambient air with the die cavity being filled with the encapsulation resin; and at least one groove formed on a surface of the lead frame that is opposite to another surface of the lead frame on which the first region is present, the at least one groove extending from an area corresponding to the first region across another area corresponding to the second region so as to reach the third region.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: November 11, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akira Oga, Hisaho Inao, Hiroshi Hidaka
  • Publication number: 20030003628
    Abstract: The lead frame of the present invention is a lead frame used in resin encapsulation of a semiconductor chip using an encapsulation mold that includes a die cavity to be filled with an encapsulation resin, the lead frame including: a first region exposed to the die cavity; a second region that is surrounding the first region and to be clamped by the encapsulation mold; a third region exposed to an ambient air with the die cavity being filled with the encapsulation resin; and at least one groove formed on a surface of the lead frame that is opposite to another surface of the lead frame on which the first region is present, the at least one groove extending from an area corresponding to the first region across another area corresponding to the second region so as to reach the third region.
    Type: Application
    Filed: December 11, 2001
    Publication date: January 2, 2003
    Inventors: Akira Oga, Hisaho Inao, Hiroshi Hidaka