Abstract: According to an embodiment, a method for estimating robustness of a trained machine learning model is disclosed. The method comprises receiving a labelled dataset, a model of an object for which defect detection is required, and the trained machine learning model. Further, the method comprises determining one or more parameters associated with image capturing conditions in the environment. Furthermore, the method comprises performing an auto extraction of one or more defects using the model of the object and the labelled dataset based on image processing. Furthermore, the method comprises generating one or more images based on the one or more parameters and the one or more defects. Additionally, the method comprises testing the trained machine learning model using the generated images. Moreover, the method comprises estimating a robustness report for the machine learning model based on the testing of the machine learning model.

Abstract: A processing system includes a first acquirer, a second acquirer, a third acquirer, an identifier, and an extractor. The first acquirer is configured to acquire a plurality of pieces of learning data to which labels have been assigned. The second acquirer is configured to acquire a learned model generated based on the plurality of pieces of learning data. The third acquirer is configured to acquire identification data to which a label has been assigned. The identifier is configured to identify the identification data on a basis of the learned model. The extractor is configured to extract, based on an index which is applied in the learned model and which relates to similarity between the identification data and each of the plurality of pieces of learning data, one or more pieces of learning data similar to the identification data from the plurality of pieces of learning data.

Abstract: The template image creation method creates a template image from a plurality of candidate images each including a target region including an image of a test object. The template image creation method includes creating at least one template image by performing position correction by pattern matching to match a position of the target region between the plurality of candidate images and sequentially combining the plurality of candidate images.

Abstract: Reliability regarding a class determination for an object is improved. Classification system includes first classification part, second classification part, and determination part. First classification part classifies first target data into at least one of a plurality of first classes. Second classification part classifies second target data into at least one of a plurality of second classes. Determination part decides whether to use one or both of a first classification result that is a classification result obtained by first classification part and a second classification result that is a classification result obtained by second classification part, and determines a class of object based on one or both of them. The first target data is image data of object. The second target data is manufacturing data regarding a manufacturing condition of object.

Abstract: Even when data that can belong to a new class that is not in an existing class is input, this data can be easily classified appropriately. Classification system includes input reception part, classification part, calculation part, determination part, and presentation part. Input reception part receives an input of target data. Classification part classifies the target data into any one of a plurality of classes. Calculation part calculates a feature amount of the target data. Determination part determines a possibility that the target data is classified into the new class based on a classification result in classification part and the feature amount of the target data calculated by calculation part. When determination part determines that there is a possibility that the target data is classified into the new class, presentation part presents a determination result of determination part.

Abstract: An image display system includes a first processor, a second processor, and a comparator. The first processor acquires a behavior estimation result of a vehicle, and generates future position information after a predetermined time passes of the vehicle based on the behavior estimation result. The second processor acquires present information about the vehicle, and generates present position information on the vehicle and a peripheral object based on the acquired information. The comparator compares the future position information on the vehicle and the present position information on the vehicle and the peripheral object, and generates present image data indicating present positions of the vehicle and the peripheral object and future image data indicating future positions of the vehicle and the peripheral object. Further, the comparator allows a notification device to display a present image based on the present image data and a future image based on the future image data together.

Abstract: An information processing system includes an incorrectness risk determiner, a safe behavior determiner, and a safety determiner. The incorrectness risk determiner makes a determination on whether or not a behavior estimation result of a vehicle carries an incorrectness risk. The safe behavior determiner classifies parameter values each indicating a travel state of the vehicle into multiple ranges based on travel safety. The safe behavior determiner also determines a safe behavior for the vehicle. By the safe behavior, the travel state of the vehicle is adjusted such that the above parameter values fall under a range with high travel safety. The safety determiner determines a behavior control of the vehicle. When the safety determiner acquires a determination including the incorrectness risk from the incorrectness risk determiner, the safety determiner selects the safe behavior.

Abstract: An information processing system includes a safe behavior determiner, clustering range controller, and safety determiner. The safe behavior determiner classifies parameter values indicating a travel state of a vehicle into multiple ranges based on travel safety. The safe behavior determiner also determines a safe behavior for the vehicle by which the travel state of the vehicle is adjusted such that the parameter values fall under a safety range with high travel safety. The clustering range controller changes a position of a boundary between the ranges according to an external environment of the vehicle. The safety determiner acquires a behavior estimation result of the vehicle and the safe behavior determined by the safe behavior determiner, and determines behavior control of the vehicle on the basis of at least the acquired behavior estimation result or safe behavior.

Abstract: An image display system includes a first processor, a second processor, and a comparator. The first processor acquires a behavior estimation result of a vehicle, and generates future position information after a predetermined time passes of the vehicle based on the behavior estimation result. The second processor acquires present information about the vehicle, and generates present position information on the vehicle and a peripheral object based on the acquired information. The comparator compares the future position information on the vehicle and the present position information on the vehicle and the peripheral object, and generates present image data indicating present positions of the vehicle and the peripheral object and future image data indicating future positions of the vehicle and the peripheral object. Further, the comparator allows a notification device to display a present image based on the present image data and a future image based on the future image data together.

Abstract: When it is detected that a write address signal and a read address signal coincide with each other during in the judgment range state, an address value of the write address signal is held to halt writing into a memory, whereby a video signal is outputted without mixing old and new frames therein. Therefore, a buffer area in the memory can be minimized, and an address control circuit can be appropriately controlled even when the frame frequency difference exceed a buffer capacity, thereby a frame synchronizer circuit that can output normal pictures is provided.

Abstract: A picture signal processing circuit capable of processing picture signals of various broadcast systems including the SECAM system, the PAL system and the NTSC system, wherein an FM demodulation circuit for demodulating a SECAM signal is used also as a portion of a burst frequency discrimination circuit. An input picture signal is demodulated by the FM demodulation circuit to obtain a frequency component thereof, and then a burst signal portion thereof is extracted by a burst extracting circuit. The extracted demodulated signal is integrated by an integration circuit, and compared with a predetermined value by a comparator, based on which the burst frequency is determined. Therefore, it is possible to instantaneously determine the burst frequency, and the circuit scale is reduced by sharing the FM demodulation circuit.

Abstract: A DD converter circuit 109 for interpolating a digital video signal which is locked to a 14.3-MHz burst clock to convert the sampling data so as to be locked to a 13.5-NHz free-run clock, and a frame memory circuit 110 for writing a digital video signal which is output by the DD converter circuit 109 on the 14.3-MHz burst clock as well as reading the written digital video signal on a 13.5-MHz clock S112 are included. Therefore, a video signal processor which can realize the rate conversion of the digital video signal without using an analog PLL circuit can be provided.

Abstract: A video signal processing apparatus processes coded data obtained by compressively coding a digitized video signal. The apparatus includes a specific component removing unit for removing specific components in the coded data. The specific component removing unit has a variable-length decoding unit for subjecting the variable-length coded data to variable-length decoding, an inverse quantization unit for inversely quantizing the processing result of the variable-length decoding unit, by using a first quantization matrix, a quantization unit for quantizing the processing result of the inverse quantization unit, by using a second quantization matrix, and a variable-length coding unit for subjecting the processing result of the quantization unit to variable-length coding. Therefore, the data quantity of the variable-length coded data can be reduced without significantly increasing the circuit scale.

Abstract: An analog-to-digital converter for converting an analog television signal to a signal in compliance with a digital encoding standard is provided.

Abstract: A DD converter circuit 109 for interpolating a digital video signal which is locked to a 14.3-MHz burst locked clock to convert the sampling data so as to be locked to a 13.5-NHz free-run clock, and a frame memory circuit 110 for writing a digital video signal which is output by the DD converter circuit 109 on the 14.3-MHz burst locked clock as well as reading the written digital video signal on a 13.5-MHz clock S112 are included. Therefore, a video signal processor which can realize the rate conversion of the digital video signal without using an analog PLL circuit can be provided.

Abstract: In digitally recording an analog video signal on a storage medium, a data selector selects first luminance and first chrominance signals output from a Y/C separator. In response, a clock select switch selects a first clock signal with a first frequency. D/A converters sample the first luminance and first chrominance signals, output from the separator, at the first frequency, thereby converting them into analog signals to be output to a monitor. In reading out a digitally recorded video signal from the storage medium, the selector selects second luminance and second chrominance signals output from a digital codec and a chroma encoder, respectively. In response, the switch selects a second clock signal with a second frequency. The D/A converters sample the second luminance and second chrominance signals, output from the codec and the encoder, respectively, at the second frequency, thereby converting them into analog signals to be output to the monitor.