Abstract: Embodiments of the present invention include a method for manufacturing a semiconductor device, in which, when a DRAM and a MOS field effect transistor that becomes a component of a logic circuit are mix-mounted on the same chip, the DRAM and the MOS field effect transistor can be provided with designed performances. After a capacitor 700 of the DRAM is formed, silicide layers 19a and 19b are formed over N+type source/drain regions 41c and 41d of MOS field effect transistors 200c, 200d and 200e that are located in peripheral circuit region 2000 and logic circuit region 3000.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a semiconductor device in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the connection layer 19 and the bit line 300 are simultaneously formed. Next, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.

Abstract: Certain embodiments of the present invention relate to a method for manufacturing a semiconductor device, in which, when a cell capacitor of a DRAM and a capacitor element in an analog element region are mix-mounted on the same chip, the manufacturing steps can be simplified. First, the lower electrodes 55a and 55b of the capacitor elements 600a and 600b, and the storage nodes 53a and 53b of the cell capacitors 700a and 700b are simultaneously formed. Next, a dielectric layer (ON layer 61) of the capacitor elements 600a and 600b, and a dielectric layer (ON layer 61) of the cell capacitors 700a and 700b are simultaneously formed. Then, the upper electrodes 69a and 69b of the capacitor elements 600a and 600b and the cell plate 67 of the cell capacitors 700a and 700b are simultaneously formed.

Abstract: The present invention relates to a pad for connecting external connection terminals such as bonding wires to IC chip. The present invention provides a semiconductor device having upper and lower electrode layers and an interlayer insulation film therebetween, the interlayer insulation film including a through hole which is formed therethrough at a given location. An interlayer connection conductor is embedded in the through hole. For example, the ball-like portion of the bonding wire may be connected to the upper electrode layer such that the ball-like portion perfectly covers the embedded conductor. Such an arrangement will not create any step. Therefore, the bonding area can be easily ensured to facilitate a further formation of more layers. The embedded metal will not be adversely affected by moisture moved into along the bonding wire. The external connection terminal may be of any suitable form such as bump electrode and film carrier.