Abstract: A semiconductor memory device comprises a ferroelectric capacitor, a voltage output circuit for outputting a first voltage for reversely polarizing the ferroelectric capacitor and a second voltage by which the polarization of the ferroelectric capacitor is not reversed, regardless of data stored in the ferroelectric capacitor, a first reference capacitor having a such a capacitance as to accumulate less charge than charge which the ferroelectric capacitor accumulates, when the second voltage is applied to the ferroelectric capacitor, a second reference capacitor having such a capacitance that as to accumulate greater charge than the charge which the ferroelectric capacitor accumulates while the ferroelectric capacitor is forwardly polarized, when the first voltage is applied to the ferroelectric capacitor, thus reversely polarizing the ferroelectric capacitor, a sense amplifier connected to the ferroelectric capacitor and the first or second reference capacitor, a reference-capacitor selecting circuit for con

Abstract: An erase gate is formed for erasing data from a floating gate in a semiconductor memory device having the floating gate and a control gate.Furthermore, in order to achieve electrical insulation between the erase gate and the control gate, an insulating film formed between the erase gate and the control gate is made thicker than an insulating film formed between the floating gate and the erase gate.

Abstract: An erase gate is formed for erasing data from a floating gate in a semiconductor memory device having the floating gate and a control gate.Furthermore, in order to achieve electrical insulation between the erase gate and the control gate, an insulating film formed between the erase gate and the control gate is made thicker than an insulating film formed between the floating gate and the erase gate.

Abstract: Disclosed is a semiconductor memory element having a semiconductor substrate of P conductivity type, source and drain regions which are of N conductivity type and formed in the substrate, a first gate insulation layer formed on the major surface of the substrate, corresponding to a channel region located between the source and drain, a floating gate electrode formed on the first gate insulation layer so as to partially overlap the channel region, a second gate insulation layer formed on the floating gate electrode, a control gate electrode formed on the second gate insulation layer so as to partially overlap the floating gate electrode, and an addressing gate electrode formed on the control gate electrode, extending to a portion of the channel region not covered by the floating gate electrode and the control gate electrode.

Abstract: A method for manufacturing a semiconductor device includes a step, after forming a polycrystalline silicon layer, of doping oxygen and/or nitrogen by ion implantation in a predetermined portion of the polycrystalline silicon layer and converting the predetermined portion into a resistive element. The polycrystalline silicon layer is formed to cover a contact hole which exposes a predetermined portion of a conductive region, that is, a doped or semiconductor region or a wiring layer formed in contact with a semiconductor body. Within this contact hole and within the region of the polycrystalline silicon layer which is in contact with the doped region or the wiring layer, the polycrystalline silicon layer is converted into the resistive element by ion implantation.

Abstract: The invention provides a method for fabricating a semiconductor device comprising the steps of: forming an insulating layer on a semiconductor substrate; selectively forming an oxidation preventive film on the surface of said insulating layer; depositing polycrystalline silicon on the entire surface of said substrate including said oxidation preventive film; selectively etching said polycrystalline silicon so as to leave said polycrystalline silicon only around the sides of said oxidation preventive film by an etching method having a directivity perpendicular to the surface of said substrate; ion-implanting an impurity for preventing inversion in said substrate using as a mask said oxidation preventive film and said polycrystalline silicon remaining therearound; and forming a field insulator film including an oxide of said polycrystalline silicon by oxidizing the surface of said substrate. A higher integration and a higher reliability of elements may be attained according to the method of the invention.

Abstract: A first level interconnection layer of substantially a given width is formed on an insulating film on a semiconductor substrate. At least two second level interconnection layers, which cross the first level interconnection layer on another insulating layer, are formed. In a step for forming the first level interconnection layer, projections are formed at each side of the first level interconnection layer between the crossings of the second level interconnection layers. The total width of the first level interconnection layer including the width of the projection is larger than the given width. After the second level interconnection layers are formed, the projections of the first level interconnection layer are removed along with any second level interconnection layer material remaining intermediate the second level interconnection layers, thereby to prevent short-circuiting between the second level interconnection layers.

Abstract: Disclosed is a method for manufacturing a semiconductor device using a polycrystalline silicon layer as an electrode and/or wire which includes a process for applying a laser light or electron beam to the polycrystalline silicon layer prior to a patterning process, thereby preventing over-etching and diffusion of impurity into the surface of a semiconductor substrate which are liable to be caused in the manufacturing processes, facilitating patterning in a desired manner, and reducing the resistance of the polycrystalline silicon layer to improve the operating speed of the device.

Abstract: A memory is formed by a first insulating layer provided on a part of the surface of a semiconductor substrate of a first conductivity type, a first electrode provided on the first insulating layer and a surface region which serves as an electrode on the semiconductor substrate facing the first electrode. A semiconductor region of a second conductivity type is formed in the semiconductor substrate spaced from the surface electrode of the substrate, for providing a connection thereof to a digit line. A second electrode is provided between the second conductivity type semiconductor region and the surface region which serves as an electrode of the semiconductor substrate via a second insulating layer. The second electrode extends over a third insulating layer provided on the first electrode, and the extended portion of the second electrode is provided with an electrode secured thereto for providing a connection of the second electrode to an address selection line.