Patents by Inventor Hisakazu Sato
Hisakazu Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7694109Abstract: When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.Type: GrantFiled: December 4, 2007Date of Patent: April 6, 2010Assignee: Renesas Technology Corp.Inventors: Toyohiko Yoshida, Akira Yamada, Hisakazu Sato
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Patent number: 7581054Abstract: In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit.Type: GrantFiled: July 17, 2007Date of Patent: August 25, 2009Assignee: Renesas Technology Corp.Inventors: Kesami Hagiwara, Takeshi Kataoka, Hisakazu Sato, Shunichi Iwata, Yoshikazu Kiyoshige, Akihiko Tomita
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Publication number: 20080133887Abstract: When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.Type: ApplicationFiled: December 4, 2007Publication date: June 5, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Toyohiko Yoshida, Akira Yamada, Hisakazu Sato
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Patent number: 7346760Abstract: When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.Type: GrantFiled: May 16, 2001Date of Patent: March 18, 2008Assignee: Renesas Technology Corp.Inventors: Toyohiko Yoshida, Akira Yamada, Hisakazu Sato
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Publication number: 20080022030Abstract: In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit.Type: ApplicationFiled: July 17, 2007Publication date: January 24, 2008Inventors: Kesami Hagiwara, Takeshi Kataoka, Hisakazu Sato, Shunichi Iwata, Yoshikazu Kiyoshige, Akihiko Tomita
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Patent number: 7162585Abstract: An address range of consecutive instructions stored in an instruction buffer is set in an address table. A determination unit determines whether an instruction address outputted from a CPU core falls within the address range set in the address table. A selector selectively outputs an instruction code stored in the instruction buffer and an instruction code stored in an instruction cache in accordance with a determination result of the determination unit. Therefore, in the case where the CPU core fetches an instruction stored in the instruction buffer, an access cycle is guaranteed and an operation of the instruction cache is stopped, thereby making it possible to improve power efficiency.Type: GrantFiled: October 17, 2003Date of Patent: January 9, 2007Assignee: Renesas Technology Corp.Inventors: Isao Minematsu, Hisakazu Sato
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Patent number: 6779098Abstract: A data processing device includes a memory system capable of a plurality of simultaneous accesses, a plurality of address generators each generating an address for accessing the memory system, an addressing register having a plurality of address registers, a data processing unit providing an operation process to the data read from the memory system, and a control unit controlling operations of the plurality of address generators and the data processing unit. The plurality of address generators can generate addresses from a common value in one address register to simultaneously read data designated by the generated addresses from the memory system.Type: GrantFiled: November 29, 2001Date of Patent: August 17, 2004Assignee: Renesas Technology Corp.Inventors: Hisakazu Sato, Isao Minematsu
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Publication number: 20040133732Abstract: An address range of consecutive instructions stored in an instruction buffer is set in an address table. A determination unit determines whether an instruction address outputted from a CPU core falls within the address range set in the address table. A selector selectively outputs an instruction code stored in the instruction buffer and an instruction code stored in an instruction cache in accordance with a determination result of the determination unit. Therefore, in the case where the CPU core fetches an instruction stored in the instruction buffer, an access cycle is guaranteed and an operation of the instruction cache is stopped, thereby making it possible to improve power efficiency.Type: ApplicationFiled: October 17, 2003Publication date: July 8, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Isao Minematsu, Hisakazu Sato
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Patent number: 6615339Abstract: A VLIW processor includes an instruction decode unit selecting one of parallel execution and consecutive execution and decoding a plurality of operation instructions included in an instruction word, and a program counter control unit controlling a value of a program counter for providing an indication for the instruction decode unit to provide as no-operation an operation instruction provided in a consecutive execution and executed prior to an operation instruction executed during a consecutive execution when branching to the operation instruction executed during the consecutive execution is introduced. This renders it possible to branch to an operation instruction executed during a consecutive execution and thus provide an enhanced efficiency of instruction-code compression.Type: GrantFiled: January 18, 2000Date of Patent: September 2, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hironobu Ito, Hisakazu Sato
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Patent number: 6560697Abstract: A data processor configured to repeatedly perform sequential execution of a plurality of instructions in a program in response to a repeat instruction in the program. The data processor includes a counting circuit configured to count every time one instruction of the plurality of instructions is executed; a judgment circuit configured to judge whether the counting circuit counts a predetermined number of times; and an instruction execution control portion configured to control an execution sequence to return to a head instruction of said plurality of instructions following a last instruction in the plurality of instructions in response to a first result output from the judgment circuit indicating that the counting circuit does not count the predetermined number of times.Type: GrantFiled: December 28, 2001Date of Patent: May 6, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hisakazu Sato
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Patent number: 6553474Abstract: A data processor in which a read operation, including misaligned data as operand data, can be performed in a single cycle. An alignment buffer having a register to hold data stored at one address in data memory is provided between the data memory and a data path unit. The alignment buffer outputs misaligned data by selecting misaligned data from data held in the register and data read from the data memory. The data held in the register is updated as word-aligned data is read out.Type: GrantFiled: January 24, 2001Date of Patent: April 22, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hironobu Ito, Hisakazu Sato
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Publication number: 20030051122Abstract: A branch trace information generation unit generates branch trace information omitting at least part of branch source information and branch destination information on a target processing based on instruction execution information showing an instruction execution status of an instruction execution unit. A trace information output unit generates and outputs trace information capable of restoring an instruction executed by the instruction execution unit from the branch trace information generated by the branch trace information generation unit. It is, therefore, possible to reduce data amount of trace information.Type: ApplicationFiled: August 8, 2002Publication date: March 13, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Hisakazu Sato
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Publication number: 20020099917Abstract: A data processing device includes a memory system capable of a plurality of simultaneous accesses, a plurality of address generators each generating an address for accessing the memory system, an addressing register having a plurality of address registers, a data processing unit providing an operation process to the data read from the memory system, and a control unit controlling operations of the plurality of address generators and the data processing unit. The plurality of address generators can generate addresses from a common value in one address register to simultaneously read data designated by the generated addresses from the memory system.Type: ApplicationFiled: November 29, 2001Publication date: July 25, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hisakazu Sato, Isao Minematsu
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Publication number: 20020095562Abstract: A shared memory shared between a parent processor and a coprocessor core includes two buffers. An access control part allows one of the two buffers to exclusively access one of either the parent processor or the coprocessor core in accordance with the buffer designation data. The buffer designation data are stored in a control register allocated to a specific address and are rewritten by the parent processor in a software manner.Type: ApplicationFiled: October 9, 2001Publication date: July 18, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Chikako Nakanishi, Hisakazu Sato
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Patent number: 6389524Abstract: A tag array retains a plurality of tag data, and performs matching of the tag data with a retrieval keyword. The tag array includes matching circuits provided corresponding to the tag data. Each of the matching circuits has CM and CC cells provided corresponding to a plurality of bits of the corresponding tag data. Each CM cell retains a corresponding bit of the tag data, and performs matching of the retaining bit with a corresponding bit of the retrieval keyword. Each CC cell, not only functions as the CM cell, but also retains a comparison condition signal input in advance, and invalidates, according to the comparison condition signal, the mismatch detected between corresponding bits of the tag data and the retrieval keyword. As a result, it becomes possible to variably set the number of bits, of an input retrieval keyword, being matched with the tag data.Type: GrantFiled: July 21, 2000Date of Patent: May 14, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hisakazu Sato
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Publication number: 20020056038Abstract: An execution control signal generation unit (910) sequentially generates an execution control signal on the basis of an instruction code (907) given through a group (908) of data latches to execute an instruction designated by the instruction code (907) when a repeat end flag (903) is not asserted (instructions have not been yet executed an execution instruction number of times) and negates all the execution control signals, regardless of the indication of the instruction code (907), when the repeat end flag (903) is asserted (instructions have been executed the execution instruction number of times). All the instructions executed while the repeat end flag (903) is asserted are negated. With this configuration, a data processor capable of executing instructions accurately a designated number of times while the instructions included in a predetermined instruction stream are repeatedly executed.Type: ApplicationFiled: December 28, 2001Publication date: May 9, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Hisakazu Sato
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Publication number: 20020026545Abstract: When fetching an instruction from a plurality of memory banks, a first pipeline stage corresponding to selection of a memory bank and a second pipeline stage corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline stages are effected in parallel, the throughput of the instruction memory can be improved.Type: ApplicationFiled: May 16, 2001Publication date: February 28, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Toyohiko Yoshida, Akira Yamada, Hisakazu Sato
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Patent number: 6345357Abstract: An execution control signal generation unit (910) sequentially generates an execution control signal on the basis of an instruction code (907) given through a group (908) of data latches to execute an instruction designated by the instruction code (907) when a repeat end flag (903) is not asserted (instructions have not been yet executed an execution instruction number of times) and negates all the execution control signals, regardless of the indication of the instruction code (907), when the repeat end flag (903) is asserted (instructions have been executed the execution instruction number of times). All the instructions executed while the repeat end flag (903) is asserted are negated. With this configuration, a data processor capable of executing instructions accurately a designated number of times while the instructions included in a predetermined instruction stream are repeatedly executed.Type: GrantFiled: July 2, 1999Date of Patent: February 5, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hisakazu Sato
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Publication number: 20010016898Abstract: Read operation including misaligned data as operand data can be performed in a single cycle. An alignment buffer (6, 7) having a register to hold data stored at one address in data memory (4, 5) is provided between the data memory (4, 5) and a data path unit (3). The alignment buffer (6, 7) outputs misaligned data by selecting it from data held in the register and data read from the data memory (4, 5). The data held in the register is updated as word-aligned data is read out.Type: ApplicationFiled: January 24, 2001Publication date: August 23, 2001Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hironobu Ito, Hisakazu Sato
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Patent number: 6144322Abstract: A variable length code processor is obtained which can perform encoding or decoding process in a plurality of variable length encoding standards. A sequence control section (5) has two control registers (VL.sub.-- MODE and VL.sub.-- CNT). A CPU (2) sets the desired value to the control register (VL.sub.-- MODE) to select a processing content to be performed by a VLC processor (4). A local memory (7) is realized by a 4K-byte RAM to store retrieval tables used in decoding or encoding process. The sequence control section (5) controls a second DCT buffer section (11), an address generating section (12), a DCT generating section (14), VLC generating section (14), a shifter section (15), a VLC buffer section (16), and a VLC pack section (17), so that the process indicated by the control register (VL.sub.-- MODE) is executable.Type: GrantFiled: February 1, 1999Date of Patent: November 7, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hisakazu Sato