Abstract: There is implemented a semiconductor memory tester capable of efficiently conducting a test on a fast memory by programming according to parameters of a device without being attended by complex program handling. The semiconductor memory tester for determining pass/fail on a memory device under test is characterized in comprising a measurement division for comparing an output from the memory device under test with an expected value at timing on the basis of a clock outputted by the memory device under test.

Abstract: There is implemented a semiconductor memory tester capable of efficiently conducting a test on a fast memory by programming according to parameters of a device without being attended by complex program handling. The semiconductor memory tester for determining pass/fail on a memory device under test is characterized in comprising a measurement division for comparing an output from the memory device under test with an expected value at timing on the basis of a clock outputted by the memory device under test.

Abstract: A timing generator, which is simple in structure, has high linearity, and operates at high speeds, is realized by varying the equivalent input capacitance of a mirror amplifier. The mirror capacitance is electrically discharged with a constant current in the saturation region and in the linear region of the amplifier. The voltage at the inverting input terminal of the mirror amplifier is compared with a constant value to produce a delay. When the delay is produced in the linear region, where the inclination of the ramp waveform is mild, the period of the delay is accurately varied by input data. Thus, the period of the delay can be set with high accuracy, and high resolution. In the saturation region, where the inclination of the ramp waveform is steep, the voltage is compared with a constant value. Thus, the timing generator is made immune to noise, even if the delay time is lengthy.