Abstract: Disclosed is a temperature measuring apparatus which is provided with: a substrate (2); a temperature sensor (3) disposed on one surface of the substrate (2); and a wire (8) disposed to electrically connect together a circuit, which detects a temperature using the temperature sensor (3), and the temperature sensor (3). In said surface of the substrate (2), a recessed section (7) having a heat capacity smaller than that of the material of the substrate (2) is formed on the periphery of the temperature sensor (3). The recessed section (7) is formed at a predetermined interval from the temperature sensor (3) such that the recessed section surrounds the temperature sensor (3) and has predetermined width and depth. Preferably, the low heat capacity zone is the recessed section (7), i.e., the groove having a recessed cross-section.

Abstract: Disclosed is a temperature measuring apparatus which is provided with: a substrate (2); a temperature sensor (3) disposed on one surface of the substrate (2); and a wire (8) disposed to electrically connect together a circuit, which detects a temperature using the temperature sensor (3), and the temperature sensor (3). In said surface of the substrate (2), a recessed section (7) having a heat capacity smaller than that of the material of the substrate (2) is formed on the periphery of the temperature sensor (3). The recessed section (7) is formed at a predetermined interval from the temperature sensor (3) such that the recessed section surrounds the temperature sensor (3) and has predetermined width and depth. Preferably, the low heat capacity zone is the recessed section (7), i.e., the groove having a recessed cross-section.

Abstract: A wafer-type temperature sensor may include a wafer for temperature detection; a circuit board bonded to one surface of the wafer for temperature detection; at least one temperature data detector provided on the one surface of the wafer for temperature detection and capable of detecting temperature data; and a temperature detecting unit mounted on the circuit board and capable of detecting a temperature of the wafer for temperature detection from the temperature data detected by the temperature data detector. Here, a difference between a linear expansion coefficient of the circuit board and a linear expansion coefficient of the wafer for temperature detection may be equal to or less than a predetermined value.

Abstract: A semiconductor device includes a memory cell part which has data input terminals and which stores data received at the data input terminals and a data bus which is supplied with data. The semiconductor device also includes a transfer circuit which is coupled between the data bus and the data input terminals and which transfers the data from the data bus to the data input terminals in response to a transfer selection signal. The semiconductor device also includes a transfer control circuit which receives a bit selection signal and outputs the transfer selection signal.

Abstract: A serial data receiving circuit comprising a most significant bit input detecting circuit (20) for providing a given control signal in synchronism with input of the most significant bit of a serial data represented by twos complement and a data converter circuit (30B) for subjecting the serial data to a sign extension data when the control signal is active and providing the resultant sign extended data as a parallel data and shifting the serial data from a low order bit to a high order bit when the control signal is inactive and providing the shifted data as a parallel data.

Abstract: A parallel multiplier consists of a systolic array of AND gates and full adders organized in stages so that each stage generates a partial product, adds it to the preceding partial products, and furnishes the sum to the next stage. A control circuit is provided that disables the outputs of each stage of the array until the operation in the particular stage is completed. The disabling of outputs reduces power consumption.

Abstract: A parallel multiplier consists of a systolic array of AND gates and full adders organized in stages so that each stage generates a partial product, adds it to the preceding partial products, and furnishes the sum to the next stage. A control circuit is provided that disables the outputs of each stage of the array until the operation in the particular stage is completed. The disabling of outputs reduces power consumption.