Abstract: According to one embodiment, each time the number of program/erase cycles of a block increases by a first number of times, a controller of a memory system measures the number of error bits of data read from a plurality of memory cells connected to each of a plurality of word lines. The controller identifies a word line group including a word line corresponding to the number of error bits which is greater than a threshold. The controller selects, based on an average number of error bits of the identified word line group, a parameter set to be applied to the identified word line group from a plurality of parameter sets. The controller changes, to the selected parameter set, a parameter set defining a program operation for the identified word line group.

Abstract: A memory controller includes an interface circuit and a processor. The interface circuit is connectable to a memory. The processor measures an erase time required to erase data from a memory via the interface circuit and measures a write time required to write data to the memory via the interface circuit. The processor controls a write time for a next write based on the measured erase time and measured write time.

Abstract: According to one embodiment, each time the number of program/erase cycles of a block increases by a first number of times, a controller of a memory system measures the number of error bits of data read from a plurality of memory cells connected to each of a plurality of word lines. The controller identifies a word line group including a word line corresponding to the number of error bits which is greater than a threshold. The controller selects, based on an average number of error bits of the identified word line group, a parameter set to be applied to the identified word line group from a plurality of parameter sets. The controller changes, to the selected parameter set, a parameter set defining a program operation for the identified word line group.

Abstract: According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to instruct to apply, to a first word line, a determination voltage that is based on a first value and a first difference value in a case where it is determined whether or not a first data value has been written in a first memory cell, to instruct to apply, to a second word line, a determination voltage that is based on the first value, the first difference value, and a second difference value in a case where it is determined whether or not the first data value has been written in the second memory cell, and to change the first difference value in a case where a first condition is satisfied.

Abstract: According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to instruct to apply, to a first word line, a determination voltage that is based on a first value and a first difference value in a case where it is determined whether or not a first data value has been written in a first memory cell, to instruct to apply, to a second word line, a determination voltage that is based on the first value, the first difference value, and a second difference value in a case where it is determined whether or not the first data value has been written in the second memory cell, and to change the first difference value in a case where a first condition is satisfied.

Abstract: A storage system includes a plurality of nodes, each of the nodes including one or more node modules each of which includes a nonvolatile storage, and a connection unit directly connectable to at least one of the nodes. The connection unit is configured to transmit an access request or an inquiry directed to a target node module, determine a length of an interval before re-transmitting the access request or the inquiry, based on a response indicating an operation status of the target node module, which is returned by the target node module in response to the access request or the inquiry, and re-transmits the access request or the inquiry after the interval of the determined length has passed.

Abstract: A storage system includes a plurality of nodes, each of the nodes including one or more node modules each of which includes a nonvolatile storage, and a connection unit directly connectable to at least one of the nodes. The connection unit is configured to transmit an access request or an inquiry directed to a target node module, determine a length of an interval before re-transmitting the access request or the inquiry, based on a response indicating an operation status of the target node module, which is returned by the target node module in response to the access request or the inquiry, and re-transmits the access request or the inquiry after the interval of the determined length has passed.

Abstract: A storage device includes a storage unit having a plurality of routing circuits networked with each other, each of the routing circuits configured to route packets to a plurality of node modules that are connected thereto, each of the node modules including nonvolatile memory, and a plurality of connection units, each coupled with one or more of the routing circuits, and configured to access each of the node modules through one or more of the routing circuits. Each of the connection units is configured to transmit an inquiry to a target node module, to initiate a write operation, and determine whether or not to transmit a write command based on a notice returned by the target node module in response to the inquiry.

Abstract: According to one embodiment, there is provided a database system in which a database server and a storage are connected via a communication line. The storage includes a data area, a second log storage area, and a second circuit. The second circuit executes a process temporarily writing data and a commitment process confirming the temporarily written data based on an instruction from the database server, and records procedures of the processes in the second log.