Abstract: A fixed point signal processor includes a general register of "2n+.alpha."-bit width coupled to an arithmetic and logic unit (ALU) of "2n+.alpha."-bit width, a first data memory of "n"-bit width, and a first selection circuit for extending the "n"-bit width data to "2n+.alpha."-bit width to output the extended data to the general register. The first selection circuit selects continuous "n" bits from the "2n+.alpha."-bit width data held in the general register, to output the selected continuous "n" bits to the data memory. A second data memory receives the "2n+.alpha."-bit width data held in the general register for saving a plurality of items of "2n+.alpha."-bit width data, and a register indicates a head position of continuous "n" bits in the "2n+.alpha."-bit width data held in the second data memory. From the "2n+.alpha.