Patents by Inventor Hisami Mitsui

Hisami Mitsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4528072
    Abstract: A hollow multilayer printed wiring board and a process for manufacturing the same are provided. The hollow multilayer printed wiring board is comprised of a plurality of printed substrates, superposed upon each other with a predetermined space therebetween. Each of the substrate has a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof. Each substrate has plated through holes in the land conductor pattern, each of which holes is in line with another plated through hole of at least one of the neighboring substrates to form a continuous through hole or an interstitial through hole. A layer of a low melting point metal is formed at least on the upper and lower end surfaces of each of the plated through holes. This layer serves as a through connection between two or more signal conductor patterns of the substrates and as an interlayer adhesion between the substrates.
    Type: Grant
    Filed: June 29, 1982
    Date of Patent: July 9, 1985
    Assignee: Fujitsu Limited
    Inventors: Keiji Kurosawa, Kenji Yamamoto, Mirsuo Yamashita, Hisami Mitsui, Ayako Miyabara, Kiyotaka Miyagawa, Takayoshi Imura
  • Patent number: 4368503
    Abstract: A hollow multilayer printed wiring board and a process for manufacturing the same are provided. The hollow multilayer printed wiring board is comprised of a plurality of printed substrates (1), (2), (3) and (4), superposed upon each other with a predetermined space therebetween each of which substrate has a signal conductor pattern (6) formed on at least one surface thereof and a land conductor pattern (7) formed on at least one surface thereof. Each substrate has plated throughholes (10) in the land conductor pattern, each of which holes is in line with another plated throughhole of at least one of the neighboring substrates to form a throughhole or an interstitial via hole (12) or (13). A layer of a low melting point metal is formed at least on the upper and lower end surfaces of each plated throughholes (10), which layer serves as a through connection between two or more signal conductor patterns of the substrates and as an interlayer adhesion between the substrates.
    Type: Grant
    Filed: January 16, 1981
    Date of Patent: January 11, 1983
    Assignee: Fujitsu Limited
    Inventors: Keiji Kurosawa, Kenji Yamamoto, Mitsuo Yamashita, Hisami Mitsui, Ayako Miyabara, Kiyotaka Miyagawa, Takayoshi Imura