Abstract: A semiconductor device which uses a fin-type semiconductor layer to form a bipolar transistor. The substrate of the device is a semiconductor substrate. A collector is a first-conductivity type impurity region which is formed in the semiconductor substrate. A base is a second-conductivity type impurity region which is formed in the surface layer of the collector. A first semiconductor layer is a fin-type semiconductor layer which lies over the base. An emitter is formed in the first semiconductor layer and its bottom is coupled to the base. A first contact is coupled to the collector, a second contact is coupled to the base, and a third contact is coupled to the emitter.

Abstract: A semiconductor device includes: a micro CMOS region including a micro CMOS and a micro interconnect that is connected to the micro CMOS; and a high breakdown voltage device region including a high breakdown voltage device that has a breakdown voltage higher than that of the micro CMOS, and drain and source interconnects that are connected to the high breakdown voltage device and have a width greater than that of the micro interconnect in a plan view. In the high breakdown voltage device region, an electrically-isolated dummy interconnect is not provided adjacent to at least the drain interconnect and the source interconnect.

Abstract: A semiconductor device which uses a fin-type semiconductor layer to form a bipolar transistor. The substrate of the device is a semiconductor substrate. A collector is a first-conductivity type impurity region which is formed in the semiconductor substrate. A base is a second-conductivity type impurity region which is formed in the surface layer of the collector. A first semiconductor layer is a fin-type semiconductor layer which lies over the base. An emitter is formed in the first semiconductor layer and its bottom is coupled to the base. A first contact is coupled to the collector, a second contact is coupled to the base, and a third contact is coupled to the emitter.

Abstract: A semiconductor device includes: a micro CMOS region including a micro CMOS and a micro interconnect that is connected to the micro CMOS; and a high breakdown voltage device region including a high breakdown voltage device that has a breakdown voltage higher than that of the micro CMOS, and drain and source interconnects that are connected to the high breakdown voltage device and have a width greater than that of the micro interconnect in a plan view. In the high breakdown voltage device region, an electrically-isolated dummy interconnect is not provided adjacent to at least the drain interconnect and the source interconnect.

Abstract: A semiconductor device includes: a micro CMOS region including a micro CMOS and a micro interconnect that is connected to the micro CMOS; and a high breakdown voltage device region including a high breakdown voltage device that has a breakdown voltage higher than that of the micro CMOS, and drain and source interconnects that are connected to the high breakdown voltage device and have a width greater than that of the micro interconnect in a plan view. In the high breakdown voltage device region, an electrically-isolated dummy interconnect is not provided adjacent to at least the drain interconnect and the source interconnect.

Abstract: A semiconductor device raises the maximum oscillation frequency fmax of the bipolar transistor. The stopper dielectric layer is formed on the substrate to cover the transistor section and the isolation dielectric. The interlayer dielectric layer is formed on the stopper dielectric layer. The base contact plug, which is formed in the interlayer dielectric layer, is located over the isolation dielectric in such a way as to contact the graft base region near its bottom end corner. Therefore, the base contact needs not to entirely overlap with the graft base region, which means that the graft base region can be narrowed without increasing the base resistance Rb and that the collector-base capacitance Ccb is reduced. Also, electrical short circuit between the graft base region and the collector region can be effectively suppressed by the stopper dielectric layer.

Abstract: A semiconductor device raises the maximum oscillation frequency fmax of the bipolar transistor. The stopper dielectric layer is formed on the substrate to cover the transistor section and the isolation dielectric. The interlayer dielectric layer is formed on the stopper dielectric layer. The base contact plug, which is formed in the interlayer dielectric layer, is located over the isolation dielectric in such a way as to contact the graft base region near its bottom end corner. Therefore, the base contact needs not to entirely overlap with the graft base region, which means that the graft base region can be narrowed without increasing the base resistance Rb and that the collector-base capacitance Ccb is reduced. Also, electrical short circuit between the graft base region and the collector region can be effectively suppressed by the stopper dielectric layer.

Abstract: A semiconductor device has an isolation area having a shallow trench isolation (STI) structure for isolating device areas for transistor elements. The isolation area for a bipolar transistor has a first annular trench encircling a n-type collector well, a second annular trench encircling the first annular trench and an annular p-type diffused region disposed between the first annular trench and the second annular trench while in contact with the annular trenches. The plurality of isolation trenches in a single isolation area prevents a dishing portion of the substrate after a CMP process without causing a short-circuit failure.

Abstract: A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the surface of the collector region, and an emitter region of a second conductivity type formed from the surface of the base region; a collector extraction region that is separated by an insulating layer and is formed in the collector region except the base region; a concave portion in the collector extraction region that is formed up to a depth where the collector region has a peak concentration in impurity distribution; and a collector extraction electrode that is connected with the collector region to extract ohmic-connecting to the bottom of the concave portion.

Abstract: An N type buried layer is buried in a P type silicon substrate. An N type epitaxial layer is formed on this buried layer. A P type intrinsic base region and an extrinsic base region are formed on the surface of the epitaxial layer. An N type emitter region is formed in the intrinsic base region. An emitter electrode is formed to contact the emitter region. A collector plug region is formed in an area separated from the extrinsic base region through a filed insulating film. A cobalt silicide film is formed on the extrinsic base region to surround the emitter electrode. An extrinsic base contact hole is formed at only one side of the emitter electrode. In the semiconductor device, the base resistance Rb and the collector-base capacity Ccb are reduced to make the maximum oscillation frequency fmax sufficiently large.

Abstract: An N type buried layer is buried in a P type silicon substrate. An N type epitaxial layer is formed on this buried layer. A P type intrinsic base region and an extrinsic base region are formed on the surface of the epitaxial layer. An N type emitter region is formed in the intrinsic base region. An emitter electrode is formed to contact the emitter region. A collector plug region is formed in an area separated from the extrinsic base region through a filed insulating film. A cobalt silicide film is formed on the extrinsic base region to surround the emitter electrode. An extrinsic base contact hole is formed at only one side of the emitter electrode. In the semiconductor device, the base resistance Rb and the collector-base capacity Ccb are reduced to make the maximum oscillation frequency fmax sufficiently large.

Abstract: Disclosed is a semiconductor device which has: a bipolar transistor comprising a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the surface of the collector region, and an emitter region of a second conductivity type formed from the surface of the base region; a collector extraction region that is separated by an insulating layer and is formed in the collector region except the base region; a concave portion in the collector extraction region that is formed up to a depth where the collector region has a peak concentration in impurity distribution; and a collector extraction electrode that is connected with the collector region to extract ohmic-connecting to the bottom of the concave portion.

Abstract: A semiconductor device which has: a bipolar transistor having a collector region of a second conductivity type formed from the surface of a semiconductor substrate of a first conductivity type, a base region of a first conductivity type formed from the surface of the collector region, and an emitter region of a second conductivity type formed from the surface of the base region; a collector extraction region that is separated by an insulating layer and is formed in the collector region except the base region; a concave portion in the collector extraction region that is formed up to a depth where the collector region has a peak concentration in impurity distribution; and a collector extraction electrode that is connected with the collector region to extract ohmic-connecting to the bottom of the concave portion.

Abstract: In a BiCMOS structure, a bipolar transistor is formed inside a the ring of a ring-shaped structure that is made of the same material as the gate electrode, and an insulation film that provides insulation between an emitter electrode and a p-type intrinsic base region is used only inside the ring-shaped structure, so that the insulation film that makes up the side wall insulation film of the CMOS transistor and the insulation film that provides insulation between the bipolar transistor emitter electrode and p-type intrinsic base region are different films.

Abstract: Implantation of a high concentration of P type impurity in an emitter electrode can be prevented during forming a source-drain of PMOS and a extrinsic base, by keeping an insulating film intact only on an emitter electrode and simultaneously patterning the insulating electrode and a gate electrode, leading to prevention of increase and dispersion of an emitter resistance.

Abstract: A method of making a BiCMOS semiconductor device in which different polysilicon layers are used to form the gate electrodes of the CMOS devices and an emitter leading electrode for the bipolar device. A first polysilicon layer forms the lower portion of the gate electrodes of the CMOS devices, while a second highly doped polysilicon layer forms a center portion of emitter leading electrode of the bipolar device.

Abstract: To provide a semiconductor device including a self-align type multi-emitter bipolar transistor wherein every collector-base isolation length can be reduced into a minimum value allowed in connection with the collector-base breakdown voltage, in a self-align type bipolar transistor having a multi-emitter structure, more than one emitter/base formation regions (114 and 115) and at least one collector leading region (106) are arranged in a single array, and extrinsic base regions (114) are connected to at least one base electrode (119c) having a contact plug (118c) provided outside the single array by way of a base leading electrode (109). Therefore, collector-base isolation lengths can be set to be a minimum length (e) determined by a collector-base breakdown voltage, enabling to minimize the collector resistance, the collector-base capacitance and the collector-substrate capacitance, as well as to minimize the element size of the bipolar transistor.

Abstract: A semiconductor device including a semiconductor substrate having thereon an element region having a surface, an element separating insulating film having an upper surface adjacent to opposing lateral sides of the element region, a silicon epitaxial layer having an upper surface formed on the surface of the element region, a polysilicon layer having an upper surface formed on the element separating film and connected to the silicon epitaxial layer, a gate insulating film and a gate electrode formed on the silicon epitaxial layer, and impurity doped source and drain regions formed in the silicon epitaxial layer. Furthermore, the upper surface of the silicon epitaxial layer is higher than or at the same level as the upper surface of the polysilicon layer. This is done by forming the polysilicon layer on a recessed portion of the element separating insulating film adjacent to the element region.

Abstract: A method of manufacturing wherein an NPN bipolar transistor, an N-type impurity region is formed in an N-type epitaxial region or an N-type well region between an N.sup.+ -buried layer region and a P-type intrinsic base region. The N-type impurity region is formed only just below the P-type intrinsic base region. The impurity concentration of the N-type impurity region is either uniform or is higher at a central portion of the region located just below an emitter diffused region than the impurity concentration at the surrounding the central portion.

Abstract: A process of fabricating a bi-CMOS integrated circuit device has a step of selectively growing doped polysilicon over a source/drain region and a part of base region exposed to contact holes formed in a silicon oxide layer without residue of the doped polysilicon on the silicon oxide layer, thereby preventing the bi-CMOS integrated circuit device from undesirable short circuit.